|Alguien dijo ...|
|La ciencia es como la tierra; solo se puede poseer un poco de ella.|
François Marie Arouet(Voltaire - 1694-1778).
Escritor y filósofo francés.
|TEXAS INSTRUMENTS OUTLINES RESEARCH ACCOMPLISHMENTS THAT WILL FURTHER
CMOS SCALING EFFORTS|
KYOTO, Japan - Texas Instruments Incorporated (TI) (NYSE: TXN), with
its research and development partners and peers, is presenting papers that describe key accomplishments on advanced
materials and manufacturing process development at the 2005 Symposium on VLSI Technology. TI's contribution
highlights a comprehensive R&D strategy designed to combine in-house initiatives with close collaboration among
industry consortia and universities to deliver the semiconductor innovations critical to TI's customers.
among the leaders in overcoming the challenges of semiconductor scaling and plans to maintain this position in the
advancement of future transistor technology," said Dr. Hans Stork, chief technology officer, Texas Instruments. "The
research presented at the VLSI Symposium will continue TI's development of high performance, low cost semiconductor
products with highly integrated system-on-a-chip (SoC) implementations."
At the VLSI Symposium,
TI and key development partners are presenting a number of key findings, including a demonstration for the first
time the scalability of fully-silicided, nickel silicide (NiSi) gates to 30nm and below. This approach promises to
ease the transition from current polysilicon gate electrodes to full-silicidation-of-polysilicon (FuSi), resulting
in cost effective integration of metal gates. Leveraging current materials and providing the least amount of changes
to today's process flow delivers a highly efficient, easy-to-integrate method to enhance performance.
TI also participates in research efforts that focus on the advancement of non-planar triple-gate devices, and
is discussing fabrication of the industry's smallest 6T-SRAM cell with multi-gate devices at the VLSI Symposium.
This accomplishment is based upon work done within the IMEC European nanoelectronics research center as part of a
sub-45nm CMOS program. TI utilizes 6T SRAM cells as the primary embedded memory in its CMOS products today.
Migrating to tri-gate non-planar transistors may extend the use of 6T SRAM cells to the 32nm node or beyond. This
approach maintains design compatibility with conventional SRAM approaches and significantly shrinks previously
designed triple-gate SRAM device cells, further improving performance and integration options.
is also presenting research through work with SEMATECH on the compatibility of non-planar multi-gate transistor
approaches with conventional CMOS approaches by introducing strain to improve the drive current of future
transistors by as much as 25 percent.
These advancements result from TI´s overall external
research strategy to evaluate the feasibility of materials, processes and device concepts in the pre-competitive
stage. TI´s in-house R&D technology development teams then shift attention to development in its manufacturing
facilities in close collaboration with customers to meet their key priorities. TI´s overall R&D addresses many
topics and focuses on closing key gaps in:
* Transistor performance scaling, including gate
* Transistor structural scaling and modifications, and channel mobility enhancement
* Interconnect performance scaling, including materials changes, and new approaches for interconnect and
* Lithography and resolution enhancement technology for feature scaling
Transistor Performance Scaling
To extend TI´s work on nitrided silicon
dioxide gate dielectrics beyond the 45nm node, new transistor materials and structural changes are also under
evaluation. These technologies promise to solve growing issues around leakage, power dissipation and heat as
transistor dimensions continue to shrink. For example, TI has led the industry in the development of Hafnium Silicon
Oxynitride (HfSiON) high-k gate dielectric materials and process technology for addressing new dielectric materials
and issues without sacrificing reliability or adding significant costs. TI participates in a number of
pre-competitive research programs that focus on advanced CMOS technology nodes including:
Three custom programs through the ATDF, a wholly owned subsidiary of SEMATECH, on manufacturability and scalability
of multi-gate Field Effect Transistors (FETs), enhanced strained silicon, and dual-work-function metal gates
* SEMATECH Front-End Processes (FEP) development
* Joint university funding
with SEMATECH and SRC for the FEP Research Transition Center
* IMEC core membership FEP research
focused on gate, junctions, silicides, strain/channel mobility, and multi-gate FETs
participation in SRC and Microelectronic Advanced Research Corporation (MARCO, an SRC subsidiary) sponsored
university research in advanced device technology
* Initiative for Nano-Materials and Processes
program at Stanford University that includes a focus on high-k gate dielectrics and metal gate electrodes
* Silicon Wafer Engineering and Defect Science (SiWEDS) Center
* Collaboration with several FEP
equipment and materials suppliers
aspects of TI´s R&D include work to identify new interconnect materials, structures and designs that enhance
performance but maintain high standards of interconnect reliability and low cost. This includes the implementation
of lower-k interconnect dielectrics, thinner and lower-k barriers and capping layers, design approaches to reduce
interconnect lengths, and advanced packaging materials and methods. Copper interconnect technology scaling research
focuses on lowering interconnect RC delays that are becoming a larger fraction of overall transistor performance.
External interconnect research includes the following affiliations:
* SEMATECH interconnect
* IMEC core membership interconnect and packaging research
* SRC and MARCO
* Collaborations with several interconnect equipment and materials suppliers
TI has a history of cost-effective innovation in
lithography, and currently leverages 193nm lithography with Resolution Enhancement Technology (RET) for 90nm device
production and 65nm ramp to qualification. TI believes that 193nm immersion lithography can take the industry
through the 45nm and 32nm nodes, and feasibility studies on taking immersion lithography beyond the 32nm node are
Work with various research organizations like SEMATECH, IMEC and SRC
includes active development of various approaches for future lithography scaling. Research in areas such as extreme
ultraviolet (EUV) lithography and alternative low-cost lithography approaches is geared toward continued decreases
in printed on-wafer dimensions and maximum throughput in wafers per hour.
TI is involved in many programs with a long-range view to maintain its process
technology and manufacturing advantage well into the future. This includes affiliation with MARCO to fund
longer-range university research through five focus centers on Materials/Structures/Devices; Functional
Nanostructures; Interconnect; Circuit Design; and Systems Design and Test. TI also participates in the recently
announced Nano-Electronics Research Corporation (NERC), a subsidiary of SRC, to research beyond-CMOS technology.
"The market continues to require technology advancements that produce highly integrated,
low power and low cost semiconductor solutions with rapid product ramp capabilities," said Dr. Stork. "TI's R&D
approach gives us the ability to efficiently evaluate and select the best materials and techniques to meet customer
demands, and deliver those advancements in high-volume manufacturing."
Miércoles, 15 Junio, 2005 - 09:18