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Norwood, MA - Analog Devices, Inc. (NYSE: ADI), a global leader in high-performance semiconductors for signal processing applications, today announced ADIsimPLL Version 3.0, a new generation of its successful phase-locked loop (PLL) circuit design and evaluation tool, as well as two new PLL synthesizers delivering industry-leading performance for the upconversion and downconversion of RF signals in wireless base station equipment. ADIsimPLL Version 3.0 builds upon the success of previous versions of the software tool by offering nine new loop filter topologies, a new VCO (voltage controlled oscillator)/reference library editor, enhanced VCO libraries, new analysis features, as well as support for six new devices. These innovative features further remove time-consuming iterations from the design process, ultimately speeding the design to market.

On the hardware side, Analog Devices is introducing the ADF4156 and ADF4002, providing low- and high-frequency PLL solutions for a wide range of wireless base station equipment, including those that support GSM, PCS, DCS, WiMAX, SuperCell 3G, CDMA and W-CDMA networks. The ADF4156 is a fractional-N PLL synthesizer operating at 6 GHz, which is one of the industry’s highest frequencies of operation for a fractional-N device. The ADF4156 is designed to implement local oscillators in the upconversion and downconversion sections of wireless transceivers and transmitters. For low-frequency requirements, Analog Devices offers the new ADF4002. Operating at 350 MHz, the ADF4002 frequency synthesizer can be used to implement clock conditioning, clock generation and IF LO generation in wireless receivers and transmitters.

“With these new PLL synthesizers and enhanced ADIsimPLL tool, Analog Devices is furthering its commitment to provide designers with innovative solutions that improve performance and help ease the development of wireless systems,” said Christian Kermarrec, vice president, RF and wireless systems, Analog Devices, Inc. “With more than 25,000 downloads since its introduction four years ago, ADIsimPLL has solidified its position as the most comprehensive design and evaluation tool for PLL circuit design available today.”

About ADIsimPLL Version 3.0
ADIsimPLL Version 3.0 is a significant upgrade to the already popular ADIsimPLL design tool. The simulator offers a comprehensive PLL design and simulation package for Analog Devices’ range of PLL frequency synthesizers, enabling rapid prototype development and design optimization.

ADIsimPLL Version 3.0 includes support for six new devices, including the new ADF4156. The tool improves the range of PLL loop filter topologies available within the simulator from 9 to 18. Many of the nine new loop filter topologies include higher order active filters, which can provide additional spurious rejection, particularly in fractional-N designs. To assist in entering and maintaining VCO and reference oscillator data libraries, ADIsimPLL Version 3.0 comes with a new dedicated VCO/Reference Library File editor, which allows browsing through a VCO or reference oscillator library file, and user entry of VCO tuning and phase noise data. In ADIsimPLL Version 3.0, the closed loop gain of the PLL is calculated and displayed on the FreqDomain page, while the phase noise plots have been enhanced to show the contributions from each of the noise sources in the PLL. The new version of ADIsimPLL comes with a substantially expanded VCO/VCXO (voltage controlled crystal oscillator) library collection, which will automatically search for suitable VCOs that meet the user’s frequency requirements. Other enhanced features include automated design of the output matching circuits for the ADF4360-8 and modeling of dither feature effects fractional-N designs. In addition, ADIsimPLL Version 3.0 is compatible with files from earlier versions of ADIsimPLL.

About the ADF4156
At 6 GHz, the ADF4156 is one of the industry’s highest frequency fractional-N PLL devices currently available on the market. The device implements local oscillators in the upconversion and downconversion sections of wireless transceivers and transmitters. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump and a programmable reference divider. There is a Σ-Δ based fractional interpolator to allow programmable fractional-N division. The INT, FRAC and MOD registers define an overall N divider (N = (INT + (FRAC/MOD))). The RF output phase is programmable for applications that require a particular phase relationship between the output and the reference. The ADF4156 also features cycle-slip reduction circuitry, which leads to faster lock times without the need for modifications to the loop filter. The device has a power supply range of 2.7-3.3V and can be powered down when not in use, resulting in overall system power reduction. The ADF4156 is pin compatible with Analog Devices’ ADF41xx family of frequency synthesizers.

About the ADF4002
The ADF4002 is a low-frequency (350 MHz bandwidth), low phase noise PLL for clock conditioning circuits in wireless systems. The device can be used to implement clock cleanup, clock generation and IF LO generation in wireless receivers and transmitters. With an N min value of one, the ADF4002 allows flexibility in clock generation/conditioning applications. The device consists of a low-noise digital PFD, a precision charge pump, a programmable reference divider and programmable N divider. The 14-bit reference counter (R Counter) allows selectable REFIN frequencies at the PFD input. A complete synthesizer can be implemented if the PLL is used with an external loop filter and VCO. The device has a power supply range of 2.7-3.3V.

Jueves, 25 Mayo, 2006 - 02:58
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