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STMicroelectronics Unveils 90nm System-on-Chip Capability for Hard Disk Drives

Geneva - STMicroelectronics today revealed its design and manufacturing capability for hard disk drive (HDD) SoC devices in 90nm technology. A new device – integrating ST’s IP (intellectual property) in the hard disk controller, the read channel, serial ATA interface (SATA) and memory – is the first such product in the market to be manufactured in a 90nm process. Functional silicon is currently being evaluated and tested, and is sourced from the world-class Crolles2 Alliance 300mm-wafer facility in Crolles, France.

The T90 Read Channel IP, developed by ST, supports data rates ranging from 300 Mbit/s up to 1.7 Gbit/s, and along with the SATA performance confirms the positioning of this design as an optimized solution for the 2.5-inch and 3.5-inch disk drives used in high-end mobile, desktop computers and servers.

Read Channels encode and decode the data flowing between the head preamplifiers and the SATA interface and memory, demanding advanced mixed-signal technologies, in which ST has extensive design and processing experience. This 90nm design is based on ST’s successful Tintoretto read-write channel architecture, which enables high data rates while low power dissipation in all HDD operating modes. T90 supports 10-bit high-rate codes and Reverse Order Coding, Media Noise Optimized Data Detection, Advanced Defect Scan, Longitudinal and Perpendicular recording and Self Servo Write. ST’s 90nm roadmap of firmware-compatible read channels will address the requirements of disk drives at all performance levels for consumer and computing application, with parts available later in the year.

The embedded hard disk controller (HDC), which manages the data flow and controls head positioning during track and seek operations, is based on proven ARM-based technology and features a 32-bit high-performance CPU core running at 450MHz.

ST announced the successful fabrication of the MiPHY (Multi-Interface PHY) Physical Layer in 90nm, last year. This macro-cell provides the high-speed SATA interface in the new chip, and can also support applications using the Serial Attached SCSI (SAS), Fiber Channel, and PCI Express serial interface standards, enabling fast design validation for different markets and reducing costs for manufacturers by optimizing engineering resources. The SATA interface is capable of 3 Gbit/s, and has shown exceptional jitter performance of less than 2ps (random) and less than 50ps (total).

“In-house development of the IP for all the functions of the hard-disk drive system-on-chip places ST in the best position to satisfy the specific requirements of high-performance drive manufacturers,” said Roberto Fantechi, General Manager of ST’s Data Storage Division. “Now, with the first 90nm SoC to reach the market, we can offer our customers increased functionality in the same silicon space, as a result of the higher gate density, coupled with lower power requirement and cost.”

Viernes, 26 Mayo, 2006 - 09:21
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