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Flexible, Single-Chip SONET/SDH Timing-Card IC From Dallas Semiconductor Meets All International Network Synchronization Standards

  DALLAS, TX -Dallas Semiconductor (NASDAQ: MXIM) introduces the DS3100, the industry's only 'Timing-Card-on-a-Chip' solution for SONET/SDH synchronization. With two digital PLLs (DPLLs), four APLLs, fourteen inputs, eleven outputs, and two complete DS1/E1 transceivers, the DS3100 incorporates all the functions required in a typical central timing-card application. When combined with an appropriate TCXO or OCXO, the device complies with all international network synchronization standards including Telcordia GR 1244 and GR-253 (Stratum 3E, 3, 4E, 4 and SMC), ITU-T G.812 and G.813, and ETSI ETS 300 462.

"The DS3100 is exciting news to our telecom equipment customers," stated Michael Smith, Managing Director of the Telecom Business Unit at Dallas Semiconductor. "The device simultaneously simplifies, shrinks, and reduces costs for the design of the central timing function in equipment with SONET/SDH ports. With the integration provided by the DS3100, timing-card designs can be completed in record time." By using the DS3100's extensive integration and flexible capabilities, board designers no longer have to design or adjust discrete PLLs or worry about sensitive analog nodes on the PCB. Gone is the need to think about transfer functions, loop equations, or complex DSP algorithms. "All of that, and more, is pre-engineered in the DS3100," Smith reiterated.

Architectural Overview

The DS3100 continually monitors up to fourteen input clocks for activity and frequency accuracy. Built-in reference selection logic automatically chooses the highest priority, valid input clock for each of two DPLLs. The T4 DPLL is typically used to convert incoming SONET/SDH clocks into derived DS1 or E1 clocks, which are sent to an external BITS/SSU through one or both of the on-chip DS1/E1 transmitters. The full-featured T0 DPLL provides timing to the rest of the system, and can be configured to take its reference from an incoming SONET/SDH clock or from an external BITS/SSU through one of two on-chip DS1/E1 receivers. The T0 DPLL provides the filtering, holdover, and phase-buildout capabilities of the system and is configurable for a wide variety of usage scenarios. Each DPLL is followed by a clock-multiplying, jitter-attenuating APLL with dividers that can provide a wide array of clock rates to the eleven clock outputs.

Technical Details

The DS3100 has a total of fourteen clock inputs: ten CMOS/TTL inputs, two LVDS/LVPECL inputs, and two analog composite-clock receivers that can also be configured as additional CMOS/TTL inputs. The clock inputs can accept clock frequencies of 2kHz, 4kHz, and N x 8kHz up to 125MHz (CMOS/TTL) or 155.52MHz (LVDS/LVPECL). The device continually monitors all inputs for activity and frequency accuracy, and validates or invalidates each according to configurable criteria.

The two integrated DS1/E1 receivers also support the 2048kHz and 6312kHz synchronization interfaces specified in ITU-T G.703. The receivers extract incoming SSM messages and provide options to automatically invalidate their recovered clocks on LOS, OOF, AIS, and other defects. Smith explained that: "The DS1/E1 receivers/transmitters are the crucial elements that set this the DS3100 apart from the competition. They make this IC a true timing-card-on-a-chip solution."

With its multicycle phase detector, the T0 DPLL can direct-lock to a number of common telecom frequencies even in the presence of significant jitter and wander on the reference clock. It also locks to any multiple of 8kHz up to 155.52MHz by locking to the reference divided down to 8kHz. Bandwidth is programmable from 0.5milliHertz to 70Hz, and a variety of damping factors are available. The device also features hitless reference switching and optional phase build-out on input transients. Several holdover-averaging modes are available, and holdover-frequency accuracy greatly exceeds the requirements for Stratum 3E compliance.

The T4 DPLL is a simplified version of the T0 DPLL, and is specifically used for frequency conversion.

Both the T0 and T4 DPLL have output APLLs that multiply the clock rate and simultaneously attenuate jitter. This DPLL/APLL combination provides the best of both architectures: the configurability and stability (over voltage, temperature, and process variation) of a DPLL, and the low jitter of an APLL.

The DS3100 provides eleven clock outputs: five programmable CMOS/TTL outputs, two programmable LVDS outputs, one 1.544/2.048MHz output, one 64kHz composite-clock transmitter, and two frame-sync pulses (8kHz and 2kHz). Each output can be sourced from either the T0 path or the T4 path. More than 60 output frequencies are available including 2kHz, 8 kHz, NxDS1, NxDS2, DS3, NxE1, E3, 6.48MHz, OC-n rates up to 311.08 MHz, and 62.5MHz and 125 MHz for synchronous Ethernet applications.

The two integrated DS1/E1 transmitters support the 2048kHz synchronization interface specified in ITU-T G.703. The transmitters can insert outgoing SSM messages in the DS1 ESF or E1 signal.

The DS3100 can be configured by an external microcontroller using any of several 8-bit parallel or SPI™ serial-bus options.

Package, Pricing and Availability

To complement the DS3100, Dallas Semiconductor also offers the DS3101, which has all the DS3100's functionality except the DS1/E1 transceivers. Both the DS3100/DS3101 are available in a compact 17mm x 17mm CSBGA package and have a -40°C to +85°C operating temperature range. Prices start at $75.00 for the DS3100, and $60.80 for the DS3101 (1000-up, FOB USA). Evaluation kits, reference design information, software drivers, BDSL files are available. See the new DS3100 complete 'timing-card-on-a-chip' solution at GlobalComm, Chicago, IL, June 4-8. Visit us at Booth #34054 for a demo and to see performance data.

Jueves, 08 Junio, 2006 - 05:16
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