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UMC Demonstrates Research Accomplishments at Symposium on VLSI Technology

2006 SYMPOSIUM ON VLSI TECHNOLOGY, Honolulu, Hawaii -- UMC (NYSE: UMC; TSE: 2303), a leading global semiconductor foundry, is presenting its key accomplishments on advanced materials and device development here today. These key findings are aimed at propelling semiconductor device scaling, and include: a simple and effective method of enhancing MOSFET performance in advanced Fully Silicided (FUSI) gate technology; new silicon germanium (SiGe) materials to provide high mobility channels and performance enhancement in p-MOSFETs; and an innovative way of creating shallow junction by utilizing strained SiGe in recessed source/drain.

"UMC is determined to maintain its position as a semiconductor industry leader by overcoming the challenges of semiconductor scaling and continuing the advancement of transistor technology," said Dr. Mike Ma, deputy division director of Exploratory Technologies for UMC's central R&D. "The research accomplishments being unveiled at the VLSI Symposium demonstrate UMC's capabilities and confidence in the development and delivery of advanced process technologies at the 45nm node and beyond. This is a vital part of UMC's strong commitment to providing system-on-a-chip (SoC) foundry solutions to our customers."

UMC is presenting a number of critical findings at the symposium that focus on closing key gaps in transistor performance scaling, namely in gate electrodes, channel materials, and approaches to scale down junction.

In the gate electrode area, for the first time, a unique strain engineering technique used to enhance performance on fully-silicided (FUSI), nickel silicide (NiSi) gates is being illustrated. FUSI gate is regarded as a promising transition between current poly silicon gate electrodes and future dual work-function metal gates that require exotic materials and complicated processing. Simply by reversing the sequence of two steps in the normal FUSI process, a unique "enveloped FUSI" scheme that results in a 10% drive current enhancement in NMOS is being proposed. Other stressing layer interactions in this scheme and performance data are also being presented.

UMC presenters are also addressing the utilization of alternative materials at the conference. For example, SiGe or Ge can replace the silicon in MOSFET channels to facilitate CMOS transistor scaling. UMC engineers are also demonstrating the promising potential of SiGe channels positioned in the (110) surface orientation as the next generation of high performance p-MOSFETs. As high as a 48% drive current enhancement on SiGe channel p-MOSFETs fabricated on (110) surfaces has been achieved and reported for the first time. In addition, when combined with a compressive stress-capping layer, the (110) SiGe channel p-MOSFETs have exhibited an extended 80% drive current gain, illustrating the promising advantage of this device architecture.

On the junction scaling side, a unique ultra shallow junction scheme featured with an integrated diffusion barrier into boron doped SiGe (SiGe:B) strained p-MOSFETs is also been demonstrated. Embedded diffusion barrier (EDB) dramatically suppresses boron out-diffusion even under excessive thermal treatment, thus resulting in superior short channel control. This approach enables the formation of ultra shallow junction and over 30% junction depth reduction, while maintaining low extension resistance using only a conventional activation process. This scheme is also compatible with other mobility enhancement techniques. Combined performance data has also been highlighted in this work.

Martes, 20 Junio, 2006 - 12:04
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