|Alguien dijo ...|
|El médico competente, antes de dar una medicina a su paciente, se familiariza no sólo con la enfermedad que desea curar, sino también con los hábitos y la constitución del enfermo.|
Marco TulioCicerón (106 AC - 43AC).
Filósofo, escritor, orador y político romano.
|Fujitsu Now Accepting ASIC Designs for Production Using its 65-Nanometer Process Technology for its North American Customers|
Sunnyvale, CA, — Fujitsu Microelectronics America, Inc. (FMA), a leader in ASIC and process technology, is now accepting ASIC designs for production using its 65-nanometer CMOS process technology, the company announced today. Fujitsu has been accepting COT customers for 65nm since the beginning of the year.
Fujitsu’s 65-nanometer process is available through the company’s CS200 series, designed for high-end, high-performance server CPU devices and networking designs, and the CS200A series, which is ideal for mobile products such as cellular phones, notebook computers, and other digital consumer products that require minimum power consumption.
Fujitsu announced earlier this year that it is adding a new fab (Fab #2 in Mie, Japan) to produce logic ICs using the 90nm/65nm process technology with 300mm wafers (see the related announcement dated January 11, 2006). The facility, which will cost more than $1 billion, will become operational by April 2007.
“Fujitsu continues its industry leadership in advanced process technology development with this announcement today,” said Kazuyuki Kawauchi, president and CEO, Fujitsu Microelectronics America. “The advantages of our process technology are compelling – low power, high density, and small gate sizes. Our process is proven and stable, and we have experienced an excellent yield ramp as the technology has been brought on line. We are pleased to offer it to our ASIC customers as well as our North American COT customers now.”
Fujitsu’s 65nm process technology integrates 11 interconnect layers and employs advanced copper and porous low-k dielectric materials to increase the device’s signal speed while reducing power consumption.
Gate lengths are approximately 30nm, which is about 25 percent smaller than gate sizes at the 90nm node. Gate oxide thickness is just 1.2nm. The smaller gate lengths and thickness combine to reduce gate capacitance and effectively lower a device’s active power. Transistor speeds are approximately 20 to 30 percent faster than 90nm speeds. SRAM cells are only half the size of those provided by 90nm technology, and the transistor density is almost doubled.
Miércoles, 13 Septiembre, 2006 - 07:27