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HILLSBORO, OR -- Lattice Semiconductor Corporation today announced it has expanded its ispClock™5300S family of in-system programmable, zero-delay, single-ended clock buffer devices with the production release of the pin-compatible ispClock5316S (16-output) and the ispClock5320S (20-output) ICs. The E2CMOS®-based ispClock5300S device family now offers programmable clock skew, termination and interface standard support in a series of five devices with 4 to 20 outputs.

"Our ispClock5300S family provides ideal low-cost clock distribution devices for any microprocessor-based system," said Stan Kopec, Lattice corporate vice president of marketing. “Using a single chip to fan out all clocks from a single source avoids timing issues due to cascading. With these new devices, the ispClock5300S family now can address all clock distribution applications which require Zero Delay Buffers and Fan-out Buffers with up to 20 outputs.”

The ispClock5300S devices support four operating configurations, including Zero-Delay Buffer Mode, Combined Zero-Delay and Non-Zero-Delay Fan-out Mode, Dual Fan-out Buffer Mode and Fan-out Buffer Mode with output dividers.

Simplified Inventory Management and Reduced Cost

The ispClock5300S family allows each pin to be individually configured, which enables a simple programmable solution that can be customized to suit the design requirements of each circuit board. The programmable interface type, skew, termination and slew rate features further reduce design effort and result in reduced board space as well as improved board manufacturability and reliability. Designers now are able to standardize on the ispClock5300S family for all their clock distribution needs, rather than using disparate clock distribution devices from different vendors. Consequently, inventory is more easily managed and costs are further reduced.

The ispClock5300S devices use three, 5-bit on-chip output counters to generate up to 3 clocking frequencies derived from one reference. Output clock frequencies can range up to 267 MHz. The high-performance Universal Fan-out Buffer has a maximum pin-to-pin skew of 100 ps, regardless of bank and frequency, while the maximum cycle-cycle (peak-peak) output jitter is less than 70 ps and the period jitter is less than 12 ps (rms). The output skew of each clock net relative to the reference input can be controlled further in delay increments of 156 ps (lead or lag) to compensate for differences in circuit board clock network trace length. The Universal Fan-out Buffers also support a wide variety of popular single-ended logic standards (LVCMOS, LVTTL, HSTL, SSTL) at a variety of voltage levels on the outputs, while reference inputs support single-ended or differential inputs. The input termination and output impedance of each output can be individually tuned to match each trace impedance, which results in clock nets with high signal integrity.

Advantages of the ispClock5300S Devices

* The Number of Clock Distribution ICs is Reduced
The ispClock5300S devices can integrate multiple types of clock distribution ICs such as Zero-Delay Buffers, Fan-out Buffers and Translators, so designers can easily select the features needed for each individual output pin in their application. In addition, the reference clock input integrates the necessary termination resistors, simplifying interfaces to popular single-ended as well as differential logic interface standards such as LVCMOS, LVTTL, HSTL, SSTL, LVDS, LVPECL, Differential HSTL and Differential SSTL at a variety of voltage levels.
* Clock Network Layout is Simplified by Compensating for Timing Delays Due to Clock Trace Length Differences
Traditionally, clock network designs are constrained to maintain equal clock trace lengths to ensure timing integrity using serpentine patterns to accommodate the extra length clock traces. Because the outputs of the ispClock5300S devices can be skewed precisely in 156 ps increments, designers can route clock patterns more conveniently and compensate for the clock edge arrival delay by skewing each output at the device.
* Circuit Board EMI Emission is Reduced by Staggering Clock Edges
To meet strict EMI standards, designers have commonly resorted to using spread spectrum clocks, which intentionally introduce jitter to diffuse peak power emissions due to coincident clock edge across multiple devices. However, the increased jitter in the clock is frequently not desirable. The fine output skew feature of the ispClock5300S devices enables designers to stagger the clock edge in steps of 156 ps, allowing the clocking edge to be spread without introducing jitter: a superior method for EMI emission reduction in many applications.

PAC-Designer® Software

The Lattice Windows-based mixed-signal software design tool, PAC-Designer® Version 4.9, provides comprehensive support for all ispClock5300S devices. Design configurations can be downloaded quickly via the PC parallel port. This version of the PAC-Designer software can be downloaded for free from

Pricing and Availability

Prices for the ispClock5316S device and ispClock5320S device start at $3.80 and $4.10, respectively, in 10KU+ quantities. Both devices are available immediately in a pin compatible 64-pin TQFP package in both commercial (0oC to +70oC) and industrial (-40oC to +85oC) temperature grades. PAC-SystemCLK5312S evaluation kits can be used with all five family members and are available through authorized Lattice distributors or on the Lattice website for $295.

Lunes, 30 Octubre, 2006 - 07:39
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