|Alguien dijo ...|
|A los hombres les encanta maravillarse. Esto es la semilla de la ciencia,|
Ralph Waldo Emerson(1803-1882).
Ensayista y poeta estadounidense.
| Zarlink Analog Foundry Introduces Sub-Micron BiCMOS Process Delivering Improved Performance in Power Management ICs|
SWINDON, UK, – Zarlink Semiconductor today announced the release of a sub-micron BiCMOS process technology specifically addressing increasing customer demand for control and intelligence in power management chips.
This process technology combines Zarlink Analog Foundry’s proven 20 V 5 GHz WPX/Y analog bipolar technology with a set of CMOS control aspects that are crucial in the fabrication of electronic components responsible for controlling power and extending battery life in consumer products, such as game consoles, mobile telephones and computers, as well as certain automotive applications.
Zarlink Analog Foundry will be discussing its new BiCMOS process technology at the 2006 FSA Suppliers Expo and Conference in Taipei, Taiwan on Wednesday, November 8th (Booth#A36).
“Our customers have been demanding a true analog bipolar BiCMOS process,” said Dr. Peter Osborne, chief technology officer, Zarlink Analog Foundry. “Most competing BiCMOS offerings are CMOS-centric with poor bipolar components. Building on our WP bipolar power management process expertise, we have integrated our 0.8-micron CMOS process to develop the only true analog bipolar BiCMOS technology available. Our next steps are to incorporate our DMOS technology onto this process to permit the development of a BCDMOS process capability.”
The Zarlink Analog Foundry continues to take advantage of the closer relationships that independent device manufacturers, fab-lite and fabless semiconductor companies are looking to develop with external foundries. The Fabless Semiconductor Association recently reported that its fabless members, in an effort to compete with or exceed the capabilities of the industry’s largest independent device manufacturers, are specifically seeking technology-rich foundries that can support next-generation chips.
“We have been executing our medium- and long-term technology roadmap to ensure existing and new customers can use our process technologies to help grow their business,” said Tony Gallagher, senior vice president, Global Operations, Zarlink Semiconductor. “We are committed to giving our many customers a competitive advantage by developing the most cost-effective, high-performance analog process technologies in the industry.”
BW series process
The BW process is a 20 V 5 GHz modular bipolar-based BiCMOS process with gate lengths of 0.8 microns. The process is available with high- and low-voltage NPN transistors and includes lateral PNP devices. The process supports both diffused and polysilicon resistors, MIS capacitors, and Schottky and Zener diodes. The standard process incorporates two levels of metallization, with an option for the top layer to be thick.
The BW process technology will be supported by a comprehensive design kit and technical support service. The Foundry’s Design Services group is a broad-based team with significant experience and expertise in IC design support, including comprehensive autographics service (chip finishing and tape out) and ESD (electrostatic discharge) consultation. The team develops and supports front-end to back-end design capabilities and models that enable IC design on industry-standard design tools. A complete “plug and play” design environment is also offered, comprising schematic capture, simulation and layout, together with a comprehensive DRC and LVS design verification suite.
Zarlink’s BW process technology will be available for low-cost prototyping using a multi-project wafer processing service. For further information, contact Steve Mace, technical marketing, Zarlink Analog Foundry at email@example.com. For more on the Zarlink Analog Foundry, visit https://foundry.zarlink.com.
Miércoles, 01 Noviembre, 2006 - 10:41