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Cadence Enterprise System-Level Verification Enables Predictable Software, Hardware and System Quality

SAN JOSE, Calif. Cadence Design Systems, Inc., the leader in global electronic design innovation, today announced a solution for enterprise system-level (ESL) verification, which for the first time combines automated hardware, embedded software and system-level verification with system-wide management and new high-performance engines. This solution, combined with the Cadence® Incisive® Plan-to-Closure Methodology, extends the traditional electronic system level approaches focused only on systems engineers and C-level tools to the rest of the enterprise with a path from an executable plan to system-level closure. It enforces the system requirements across all engineering functions doing design and verification from an abstract system-level model and verification plan to in-system IP verification, systems integration, validation and closure.

The result is predictable system-level quality and 50 percent reduction in time to market for complex system-on-chip (SoC) designs for consumer, networking and wireless electronics markets where significant amounts of embedded software are part of the design and verifying hardware/software interactions are a major issue.

The Cadence ESL verification solution is comprised of three new system-level innovations spanning the full enterprise:

Automated hardware, embedded software and system-level verification—applies proven techniques from advanced hardware verification to embedded software and system-level verification
System-wide management—extends proven hardware plan and metric-driven verification management to embedded software and system-level verification
High-performance engines—enables new higher performance emulation and SystemC simulation models to be accessed from system-wide management and the hardware/software automation environment

These three new system-level innovations are enabled by the Incisive Enterprise Simulator with ESL option, the Incisive Enterprise Manager, a new generation Incisive Palladium® III accelerator/emulator and the Plan-to-Closure Methodology. (See today's press release, "Incisive Palladium III Productivity Enables High Performance Enterprise System-Level Verification".) Empowering extended teams, including project managers, systems architects, logic systems engineers, logic designers, software engineers, verification engineers and system validation teams, the Cadence ESL verification solution allows the project team to perform in-system verification at the block, chip and full system levels within a common system context.

"As the industry moves toward 45 nanometer technology, we are seeing significant product life cycle cost and profit challenges for advanced SoCs. These system-level complexities will continue to increase the demand for enterprise-wide verification solutions that link together the hardware, software and system integration with the validation process, said Dr. Handel H. Jones, chief executive officer of International Business Strategies, Inc. in Los Gatos, Calif. "Cadence's approach of applying efficient hardware verification techniques at the system-level, as well as offering verification solutions at each step of the design phase can decrease development times and costs in addition to reducing the need for re-spins."

"Thorough testing and quality assurance of hardware and software interactions is a major verification challenge at ST," said Laurent Ducousso of STMicroelectronics. "Built on top of Cadence proven automated hardware verification solution, as well as the new Palladium III high performance emulator, the new Cadence solution provides mechanisms to allow a unified verification environment to control and monitor both hardware and embedded software simultaneously, allowing multi-specialists to target these cross boundary issues with well-proven advanced verification techniques."

Automated Hardware, Software and System-Level Verification
The Cadence ESL verification solution is the first to deliver automated hardware, software and system-level verification, which enables constrained-random and coverage-driven techniques to automate the generation of system scenarios. These scenarios uncover costly functional bugs using combinations of software routines, hardware functions and system-level interface transactions.

A generic software adaptor works with the system-level automation technology allowing SoC software to be exercised on a range of high-performance engines without changing the environment. New software-based Universal Verification Components (UVCs), a new form of verification IP (VIP), provide software sub-routines in various sequences to the automation environment and measure coverage of those function calls. Finally, an upgraded SimVision simulation interface facilitates fully integrated hardware and software debug and failure analysis.

System-Wide Management
The Cadence ESL verification solution extends proven hardware plan and metric-driven verification management to embedded software and system-level verification and includes the ability to capture executable system-level verification plans, track and analyze all system-wide verification activities, and aggregate total system-level coverage metrics. These management capabilities will result in a much more predictable system-wide verification process, greater utilization of the broad team resources, and much higher quality assurance of hardware, software and the entire system.

High-Performance Engines—Featuring New Incisive Palladium III
The Cadence ESL verification solution supports full integration with the highest performance emulation and SystemC simulation engines, including the new Incisive Palladium III, which provides up to 2 MHz performance, up to twice the run-time and an order of magnitude FullVision debug performance improvements over the previous generation. Palladium III also comes with a high-speed transaction interface to the constrained-random, coverage-driven ESL automation capabilities of the Incisive Enterprise Simulator. This same automation environment can be linked with a native, mixed-language, high-speed transaction interface to a SystemC model with speeds ranging from tens of KHz to MHz.

"The Cadence enterprise system-level verification solution delivers an integrated approach combining automation, management and performance. With the introduction of this capability, Cadence is pioneering system-wide process automation and closure across multiple specialists," said Steve Glaser, corporate vice president of marketing, Verification Division at Cadence. "This is a major step in our continued effort to provide block-, chip- and system-level predictability and quality of hardware, software and complete systems, as part of the Cadence Plan-to-Closure Methodology."

Supporting Ecosystem Bridges System-Level Design
Cadence has fostered a strong ecosystem supporting the ESL verification solution that includes industry standard processors and software debuggers, Cadence UVCs, accelerated VIP and SpeedBridge rate adapters. The solution is also integrated with industry-standard software debuggers from Green Hills Software, Wind River Systems, Inc., Freescale Semiconductor and ARM and works with FS2 (MIPS) hardware/software cross-probing debug solutions.

Sábado, 09 Diciembre, 2006 - 10:39
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