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STMicroelectronics Uses IEDM 2006 to Present Latest Innovations in CMOS Imaging, Non-Volatile Memory and Process Technologies

Geneva, - STMicroelectronics, one of the world’s most innovative semiconductor companies, will participate as presenter or co-author of 11 papers at this year’s International Electron Devices Meeting (IEDM) in San Francisco during December 11 – 13, 2005. ST’s top-rank contributions ranged from mainstream CMOS technology to Non-Volatile Memories and CMOS image sensors.

“The scale and scope of our presence at this year’s IEDM once again demonstrates ST’s R&D strengths: its ability to spearhead innovation, to drive the industrialization of leading-edge semiconductor technologies, and, most importantly, to work in close cooperation with partners, including the Crolles2 Alliance and world-class research institutes from many countries,” said Laurent Bosson, Executive Vice President, Front-End Technology and Manufacturing at STMicroelectronics.

In the field of Non-Volatile Memories, Phase-Change Memory (PCM) is a leading candidate for future generations and a joint paper by ST and Intel discusses the electrical characterization of anomalous cells in PCM arrays. The paper reports the discovery of two potential failure mechanisms and proposes new approaches for improvements. (Monday December 11, 2006 – 4.05pm - 2.7 - Electrical Characterization of Anomalous Cells in Phase Change Memory Arrays)

In the floating-gate NVM area, oxide defects play a major role in reliability by, determining stress-induced leakage current and charge-trapping effects. Extraction of the statistical properties of traps is a fundamental step for the optimization of future Flash technologies and a paper by ST and research partners at Milan Polytechnic presents a new physical model based on a statistical analysis of random telegraph noise. (Tuesday December 12, 2006 - 2:45pm - 18.2 Defects Spectroscopy in SiO2 by Statistical Random Telegraph Noise Analysis)

ST will co-present with EPF Lausanne a paper describing a new memory concept based on MEMS technology. A novel Suspended-Gate MOSFET scalable 1T memory architecture is proposed to achieve semi-volatile memory, between RAM and FLASH, while lowering the power consumption. The developed technology makes the hybrid electro-mechanical device compatible with advanced CMOS and opens new perspectives for embedded memory. (Tuesday December 12, 2006 - 2:20pm - 19.1 1T MEMS Memory Based on Suspended Gate MOSFET)

Reinforcing its leadership in CMOS Image sensor technology, ST will unveil an innovative process for 1.75µm pixel image sensors that delivers substantial improvements in key parameters such as light conversion gain, saturation voltage, sensitivity, dark current and noise. The Cu-based process is particularly suitable for mobile phone applications at low light levels and a full 3MP demonstrator with 1.75µm pixel pitch has been successfully designed, fabricated and characterized. (Monday December 11, 2006 – 2:50pm - 5.4 Fully Optimized Cu Based Process with Dedicated Cavity Etch for 1.75μm and 1.45μm Pixel Pitch CMOS Image Sensors)

CEA-LETI, together with ST and other research partners, will present a paper on the fabrication of an above-IC CMOS image sensor with 3µm pixel pitch built with amorphous silicon. Experimental results demonstrate an unparalleled enhancement in amorphous silicon reliability under high levels of illumination, achieved by material, process and pixel design improvement. (Monday December 11, 2006 - 3:40pm - 5.6 A Highly Reliable Amorphous Silicon Photosensor for Above IC CMOS Image Sensor)

In the field of process technology, a collaboration on advanced devices between the teams of STMicroelectronics, CEA-LETI and Freescale Semiconductor has resulted in a paper that compares for the first time the scalability of Physical- and Chemical-Vapor-Deposition (PVD and CVD) TiN on HfO2 as a gate stack for FDSOI cMOSFETs down to 25nm gate length and width. (Tuesday December 12, 2006 - 4:50pm - 23.7 Comparative Scalability of PVD and CVD TiN on HfO2 as a Metal Gate Stack for FDSOI cMOSFETs Down to 25nm Gate Length and Width)

Another paper co-authored by ST, CEA-LETI and IMEC will describe a novel 3D integration process for highly scalable nano-beam stacked-channels GAA (Gate-All-Around) FinFETs with HfO2/TiN gate stack, resulting a fivefold increase in current density per layout surface compared to planar transistors with the same gate stack. (Wednesday December 13, 2006 - 2:50pm - 38.4 Novel 3D Integration Process for Highly Scalable Nano-Beam Stacked-channels GAA (NBG) CMOSFETs with HfO2/TiN Gate Stack)

Together with IMEC, NXP, TI, and Panasonic, ST has co-authored an invited paper on what is likely to be the lowest cost metal-gate candidate for low power CMOS: the Ni-TOSI option. This work reports the first comprehensive evaluation of FUSI (fully silicided) gates for manufacturability, covering the key aspects of integration, process control, reliability, matching, device design and circuit-level benefit. Thanks to a selective and controlled poly etch-back process, dual work-function Ni-based FUSI CMOS circuits with record ring oscillator performance have been achieved, meeting the ITRS 45nm node requirement for low power CMOS. (Tuesday December 12, 2006 - 9:55am - 10.3 Ni-based FUSI Gates: CMOS Integration for 45nm Node and Beyond)

Going deeper in decananometric scale MOSFETs physics, a work in collaboration with Philips, CEA/LETI and IMEP analyses a new challenge for sub-50nm technologies: the carrier mobility degradation for very short transistors. A cause is identified thanks to low temperature mobility measurements and insights into the transistor physics, and an optimization path is proposed. (Wednesday December 13, 2006 - 9:55am - 26.3 Unexpected Mobility Degradation for Very Short Devices: A New Challenge for CMOS Scaling)

In the “Novel Device Technologies” section, a paper co-authored by ST and two research partners presents new results on silicon I-MOS devices, where an adaptation of a conventional CMOS process makes the source and drain of opposite doping types.

Fabricated devices are fully functional down to 55nm of gate length and the smallest device, reported has a 17nm gate length. For all devices, the maximum current is only limited by the contacts destruction, positioning the measured value of 4700-microamps/micron among the highest ever reported for a MOS device. In addition, it is shown that the extrapolated Ion/Ioff figure of merit is close to complying with the specifications imposed to the HP (High-Performance) flavor of the ITRS’05 roadmap. (Monday December 11, 2006 - 2:00pm - 6.2 High Current Drive in Ultra-Short Impact Ionization MOS (I-MOS) Devices)

Finally, the partners of the Crolles2 Alliance, ST, Freescale and NXP, will present a paper confirming its 45nm low-cost low-power CMOS Platform aimed at early production start in Q4 2007. Based on the early introduction of High NA 193nm Immersion Lithography, the Alliance demonstrated HD (High-Density) SRAM functionality with 40nm devices. The SRAM density is twice the equivalent 65nm HD SRAM offer, both for high speed and low leakage cells. Other key features include the use of advanced stressor techniques, a triple gate oxide process for high-speed applications and an intermetal dielectric K value of 2.5, allowing performance to be maintained after stacking 6 to 10 levels of copper. (Wednesday December 13, 2006 - 10:20am - 27.4 A Cost-Effective Low Power Platform for the 45-nm Technology Node)

Lunes, 11 Diciembre, 2006 - 08:26
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