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|Cadence Encounter RTL Compiler Extends Technology Lead in Synthesis, Increases Quality of Silicon|
SAN JOSE, Calif. , Cadence Design Systems, Inc. , the leader in global electronic-design innovation, today announced enhancements to the Cadence® Encounter® RTL Compiler solution with advanced global synthesis technology that allow designers to produce more competitive and cost-effective semiconductor devices.
The new Encounter RTL Compiler version 6.2—available in L, XL, and GXL offerings—includes breakthrough global-focus algorithms that improve the quality of silicon (QoS) results including timing, power and area up to 10 percent, and reduces synthesis runtimes by as much as 50 percent.
Through hundreds of tapeouts, Encounter RTL Compiler global synthesis has proven to deliver improved performance, smaller die sizes, lower power consumption and faster design closure through place and route. These results are consistent across all types of designs, providing quality of silicon results not achieved by any other EDA vendor. Encounter RTL Compiler global synthesis offers multi-objective, multi-voltage capability for meeting frequency targets, minimizing area, and meeting power requirements early in the design stage.
"Data from our internal test cases and over 20 customer designs show that Encounter RTL Compiler with advanced global synthesis technology delivers timing and area improvements averaging 5 percent above earlier versions; power improvements averaging 10 percent; and run-time improvements averaging 30 percent, and as high as 50 percent," said Pradeep Fernandes, vice president of synthesis R&D at Cadence. "The bottom line is, designers can make their chips faster and more cost competitive than ever before with the newly-enhanced Encounter RTL Compiler global synthesis."
Designers in a variety of markets, including wired networking, wireless, storage, graphics, and consumer processors, can benefit from these enhancements. In fact, Cadence has already received test results from each of these markets. One such device was the Chesapeake network processor designed by Bay Microsystems.
"Encounter RTL Compiler XL with advanced global synthesis technology was a vital part of our success in developing our Chesapeake network processor," said Tony Chiang, senior vice president of Bay Microsystems. "We were able to synthesize 1.5 million instance blocks top-down, which made our designers more productive and helped speed our time-to-market. And, the multi-objective synthesis of Encounter RTL Compiler helped us meet our aggressive frequency targets while minimizing area. The new 6.2 release provided area and power reductions of about 5 percent, and significant runtime reductions over our current release, so we look forward to taking advantage of these improvements."
"We use Encounter RTL Compiler global synthesis because it has the fastest turnaround times and produces the best netlist for physical implementation," said Eka Laiman, principal engineer at Magnum Semiconductor, a leading provider of ICs, software and platforms for recording and managing audio and video content. "With the 6.2 release we have seen a 50 percent runtime reduction, along with significant area and power reduction. This will help us become even more competitive in the digital video IC market."
These new advanced global synthesis capabilities are available in the L, XL, and GXL configurations of the Encounter RTL Compiler segmented product
Martes, 19 Diciembre, 2006 - 09:09