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FPGA with Features and Performance Unprecedented in a Low-Cost

HILLSBORO, OR - Lattice Semiconductor Corporation today announced that its LatticeECP2M™ FPGA family has been named “Product of the Year” by Electronic Products magazine.

Product of the Year recognition from Electronic Products magazine is among the most prestigious awards in the electronics industry due to the longevity of the competition (every year for the past 31 years) and its selectivity: each year the editors of Electronic Products select only a handful of products from among the thousands introduced. Products are judged against three criteria:

* A significant advancement in a technology or its application.
* Innovative design.
* A substantial achievement in price/performance.

"Our readers are constantly seeking information about new products and components that can enhance the performance and cost-effectiveness of their designs," said Jim Harrison, West Coast editor for Electronic Products magazine. "To obtain the Product of the Year award means the ECP2M has delivered a truly exceptional combination of the two. Lattice has really done their homework and brought to market a device that really hits this sweet spot."

“2006 was a year of milestone product introductions for Lattice, including our 90nm LatticeSC™ Extreme Performance™, 90nm LatticeECP2™ and 90nm LatticeECP2M FPGA families,” said Stan Kopec, corporate vice president of marketing. “The enthusiastic customer response to the LatticeECP2M FPGA family is evidence of the market’s demand for FPGAs that are low-cost yet deliver premium features and performance. We are honored and delighted that Electronic Products magazine has recognized the significance of the LatticeECP2M FPGA family.”

About LatticeECP2M FPGAs

LatticeECP2M FPGAs are an innovative response to the broad range of customers who have been clamoring for low-cost SERDES capability for chip-to-chip and small form-factor backplane applications. The LatticeECP2M family maintains all of the compelling features of the 90nm LatticeECP2 family that are required for high-volume, cost-sensitive applications, while dramatically increasing memory capacity (ranging from 1.2 Mbits to 5.3 Mbits) and DSP resources (ranging from 24 to 168 multipliers). The five devices in the series, ranging in size from 19K to 95K lookup tables (LUTs), provide an inexpensive alternative for implementing PCI Express, Ethernet, Serial RapidIO and CPRI/OBSAI interfaces, and each SERDES channel operates on just 100mW at full speed. The SERDES integrated into the LatticeECP2M devices has been engineered as a quad-based architecture with 1 to 4 quads (up to 16 SERDES channels maximum per device), depending on the size of the device. Each quad features 4 SERDES channels (4 complete TX and RX channels), with each channel featuring power consumption as low as 100mW and supporting data rates from 270 Mbps to 3.125 Gbps. A flexible PCS layer that includes 8b/10b encoding, an Ethernet link state machine and rate matching circuitry also are built onto the chip. The SERDES/PCS combination is designed to support today’s most common packet-based protocols, including PCI Express, Gigabit Ethernet, Serial RapidIO and wireless interface standards (OBSAI and CPRI).

Martes, 02 Enero, 2007 - 05:52
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