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Ubicom Chooses Cadence Incisive Formal Verifier for Logic Design Team Verification

San Jose, Calif., Cadence Design Systems, Inc. today announced that Ubicom, a leading developer in communications and media processor (CMP) and software platforms, has incorporated the Cadence® Incisive® Formal Verifier solution into its overall design flow.

This has allowed Ubicom to streamline the overall time needed to verify some of their most advanced products that drive interactive applications and multimedia content for the digital home.

"We are very pleased with the Incisive Formal Verifier technology as part of our overall assertion-based verification methodology," said Jon Gibbons, vice president of engineering at Ubicom. "Today's networking devices are pushing the envelope in the area of design and system-level verification needs. And Formal Verifier is the only technology on the market we felt could improve our verification process and offer an easy path for our designers to get involved in verification much earlier."

The Incisive Formal Verifier solution was selected by Ubicom due to a combination of factors including performance and capacity, ease of use, comprehensive methodology, ease of flow integration, ease of adoption, and support infrastructure. Formal Verifier technology enabled Ubicom to identify bugs that had eluded simulation-based verification. With assistance from Cadence, Ubicom quickly built up a strong foundation and a much improved process for design team verification, including integration of best-practices related to deployment and proliferation of an assertion-based verification flow.

Ubicom plans to be up and running formal assertion verification weeks or even months prior to simulation on some of their most advanced and unique multithreaded networking processors.

Part of the Cadence Logic Design Team Solution, "Design with Verification," Incisive Formal Verifier technology provides an efficient way to perform early verification, and provides usability synergies with the Incisive Design Team Simulator. The formal technology exposes most functional bugs early in the development of the design, including complex corner-case bugs, protocol compliance issues, and verification of problem-prone areas, significantly reducing quality risks.

The software also goes one step further by validating and offering proper design fixes for users. This enables designers and verification engineers to verify individual blocks months prior to testbench simulation, and to complement traditional verification techniques. The solution also speeds up design integration and validation efforts, adding further to faster turn-around and an overall productivity boost for engineering teams.

"We are clearly seeing strong Incisive Formal Verifier adoption," said Mitch Weaver, corporate vice president of the Verification Division at Cadence. "The easy-to-adopt, integrated, assertion-based verification flow, part of the Plan-to-Closure methodology, delivers clear benefits to our market-leading customers, such as Ubicom, including improved project schedules and greater predictability."

Ubicom develops CMP and software platforms that address the unique demands of real-time interactive applications and multimedia content delivery in the digital home.

Miércoles, 03 Enero, 2007 - 09:12
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