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Customer Adoption Rate of Cadence SystemVerilog Triples and Moves Into Mainstream Development

SAN JOSE, Calif. , Cadence Design Systems, Inc. the leader in global electronic-design innovation, today announced that its verification solutions based on SystemVerilog grew over the last year from approximately 40 customers experimenting with the language to more than 150 customers using the language in either prototype projects or mainstream product development.

The company attributed the accelerated growth rates to the dramatic increase in SystemVerilog language support, extended multi-language functionality, the Cadence® Incisive® Plan-to-Closure Methodology, and newer advanced SystemVerilog verification technologies.

A recent user survey by Cadence indicated which customers were using different portions of SystemVerilog today. Among those customers, approximately 57 percent are using design constructs, 60 percent are using assertions, and 57 percent are using testbench constructs. More than 50 percent of the 150 customers using SystemVerilog with the Cadence Incisive verification platform and solutions are using it for mainstream product development.

"SystemVerilog verification is an important aspect of our overall verification strategy, and it will help us maintain the quality our wireless customers demand," said Simon Knowles, vice president, Silicon, at Icera. "We have been impressed with the Cadence verification expertise in SystemVerilog and their comprehensive infrastructure of metric-driven verification solutions."

"The key factor that made us decide to use the Incisive Design Team family came after we evaluated the SystemVerilog portion against competing solutions on the market," said Ron Eliyau, Tulip Division general manager, at Saifun. "Verification is critical to maintaining the capability and high reliability that differentiates our non-volatile memory products. With Cadence SystemVerilog products, the Incisive Plan-to-Closure Methodology, and the expertise of the Incisive verification team, we replaced 2000-line directed tests with 20-line SystemVerilog randomized tests."

"The Incisive Design Team family provided the SystemVerilog automation we needed to reduce our verification time by over 40 percent," said Vishwanath H., Verification lead at inSilica. "Cadence and the Incisive Plan-to-Closure Methodology for SystemVerilog enabled us to increase our quality and productivity and improve our methodology for future projects."

"We're excited to see the recent momentum around our verification solutions based on SystemVerilog," said Steve Glaser, corporate vice president, Verification Division at Cadence. "Our customers will only move to SystemVerilog if they have compelling reasons to do so. The evolution of our Plan-to-Closure Methodology, mixed-language support and advanced verification technologies has inspired a growing number of our customers to move to our SystemVerilog solutions."

Lunes, 08 Enero, 2007 - 09:31
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