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Synopsys and UMC Enhance 90-nm Reference Flow with Advanced Low Power and Design for Test Capabilities

MOUNTAIN VIEW, Calif., and HSINCHU, Taiwan, - Synopsys, Inc., a world leader in semiconductor design software, and UMC, a world-leading semiconductor foundry, today announced that the two companies have collaborated to add new capabilities to the reference design flow based on Synopsys' GalaxyTM Design Platform for UMC's 90-nanometer (nm) process.

The advanced low-power design flow, initially introduced in November 2005 (see, now includes an automated multiple voltage (multi-Vdd) capability that can reduce dynamic power and leakage power dissipation significantly. New design-for-test (DFT) capabilities have also been added to the flow, and existing design for manufacturing (DFM) capabilities were validated with UMC's libraries. These additions help IC companies reduce risk and achieve predictable success for complex low-power designs.

The RTL-to-GDSII reference flow helps designers address multi-voltage design challenges such as dynamic power and leakage, which are especially important in 90-nm designs. The reference flow features level shifter insertion, placement, optimization and verification, as well as voltage area (VA) creation and VA-aware physical optimization, clock-tree synthesis and routing. The timing closure flow includes signal integrity (SI) prevention, repair and sign-off with multi-voltage physical verification. In addition, the flow includes full-chip power analysis and power network analysis to ensure the power integrity of the design. Synopsys' DFT MAX scan compression automation solution is now included in the reference flow to enable higher test quality and to reduce tester application time. The 90-nm reference flow also features Synopsys' DFM technology for redundant via insertion, via-farm/via-array rules and timing-driven metal fill.

To validate the effectiveness of the reference flow, design consultants from Synopsys' Professional Services collaborated with UMC engineers to design a test chip with an open source 32-bit RISC microprocessor core. The test chip, which was validated with UMC's library, was partitioned into multiple voltage regions and implemented using the advanced low-power reference flow. The core consisted of a SPARC-V8 compliant 32-bit RISC CPU, industry standard AMBA system buses, 10/100 Ethernet MAC and standard PCI interfaces. The chip is highly configurable and expandable for additional digital and/or analog/mixed-signal intellectual property (IP) modules.

"Our successful partnership with Synopsys gives our customers access to a validated 90nm reference flow that reduces risk and speeds time to market," said Ken Liou, director of the IP and Design Support division at UMC. "Our continued collaboration with Synopsys Professional Services ensures that the performance and capabilities of the Galaxy Design Platform will work smoothly in UMC's most advanced process flows."

"Synopsys works closely with world-class foundries like UMC to ensure that our mutual customers have access to a proven flow that targets low power and DFM requirements," said Rich Goldman, vice president of Strategic Market Development at Synopsys. "This collaboration helps ensure that Synopsys' Galaxy Design Platform offers UMC customers a complete, reliable RTL-to-GDSII design flow. We will continue to work with UMC to address future challenges as we move to even deeper submicron processes."

The UMC/Synopsys reference design flow is available today and can be accessed from UMC's website at The reference design flow was jointly developed by UMC and Synopsys Professional Services.

Martes, 09 Enero, 2007 - 07:04
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