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Lattice Releases Reference Design For GPON Burst Mode Receiver

Lattice Semiconductor Corporation today announced the availability of its PURESPEED™ I/O Burst Mode Receiver (BMR) FPGA Reference Design for Gigabit Passive Optical Networks (GPON). This reference design uses Lattice's unique Adaptive Input Logic (AIL) block found on its LatticeSC™ FPGAs and LatticeSCM™ FPGAs (collectively, the LatticeSC/M family) to rapidly establish stable clock to data timing relationships within the fast lock times specified in the GPON ITU-T G.984.1 specification, which requires the Optical Line Termination (OLT) to lock to incoming data within 50 bit times.

"The ability of our PURESPEED I/O System to function as an OLT Burst Mode Receiver using the AIL block is one of the genuine differentiators of the LatticeSC/M family," said Stan Kopec, Lattice corporate vice president of marketing. "Terminating upstream GPON traffic using a mere 150mw of power is a huge advantage to customers when compared to 400mw for the nearest programmable solution and 1w for standard products. With this solution, our customers are able to terminate multiple GPON channels on a single FPGA in a remarkably compact 256 BGA package."

About GPON

GPON is an important "first mile" access technology that allows carriers to offer enhanced broadband content to homes and businesses by leveraging fiber optic connections to the customer's premises. In the upstream direction, the OLT receives data from the ONT (Optical Network Termination) in bursts, and so needs to quickly lock on to data as it is sent. Traditional Ethernet and SONET CDRs (Clock and Data Recovery) have inherently long lock times and latencies, making them difficult or impossible to use in the upstream direction. The Lattice BMR solution leverages the fast locking, low latency AIL circuitry in the industry-leading PURESPEED I/O to perform the data recovery, making it the smallest footprint and lowest power FPGA-based BMR solution available today.

AIL is one of the key building blocks within the PURESPEED I/O architecture featured on the LatticeSC/M family of FPGAs. Other key components of the PURESPEED I/O include:

* High performance I/O buffers with dedicated logic to provide seamless and robust parallel source synchronous I/O solutions
* Highly flexible, built-in shift register and DDR/SDR Mux/Demux logic
* Dedicated Clock Divider circuitry for by-2 and by-4 clock division

Customers can learn more about this solution from the webinar, "Lattice GPON Solutions," which is archived on the Lattice website. Additional information, including the reference design, a GPON Application Note, Reference Design User's Guide and GPON presentation is available at

About the LatticeSC/M FPGA Family

The Extreme Performance™ LatticeSC family is designed to provide the unsurpassed performance and connectivity essential for high-speed applications. Fabricated on Fujitsu's 90nm CMOS process technology utilizing 300mm wafers, LatticeSC FPGAs are packed with features that accelerate chip-to-chip, chip-to-memory, high-speed serial, backplane and network data path connectivity.

Integrated into the LatticeSC devices are high-channel count SERDES blocks supporting 3.8Gbps data rates, PURESPEED parallel I/O providing industry-leading 2Gbps speed, innovative clock management structures, FPGA logic operating at 500MHz and massive amounts of block RAM. Lattice's unique Masked Array for Cost Optimization (MACO™) embedded structured ASIC blocks also are available on the LatticeSCM devices, delivering pre-engineered, standard-compliant IP functions such as SPI4.2, Ethernet MAC and PCI Express control functions developed by Lattice to shorten end-system time to market.

Miércoles, 18 Abril, 2007 - 12:30
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