Foros Electrónica
Alguien dijo ...
Las ciencias aplicadas no existen, sólo las aplicaciones de la ciencia.

Louis Pasteur(1822-1895).
Químico y bacteriólogo francés.
Sitios recomendados
STMicroelectronics Moves 128-Mbit NAND Flash Chip to 90nm Production Technology

  Geneva – STMicroelectronics announced that production of its 128-Mbit NAND Flash device – the NAND128W3A2BN6E – has been transferred to 90nm process technology. The shrink to 90nm reduces both the cost and the power consumption of the memory chip, which is widely used in cost-sensitive consumer equipment such as Digital Still Cameras, Audio Recorders, PDAs, Set-Top Boxes (STBs), Printers, and bundled Flash Cards. The NAND128 is currently the only 128-Mbit Flash memory on the market to be produced in 90nm technology. The new chip confirms ST’s commitment to continuing product development of its low density ‘Small-Page’ NAND Flash memory products, in support of customers already using the family in volume production. The NAND128W3A2BN6E is a 3V product, in a TSOP package, intended for consumer applications. Other family members – the 256-Mbit, 512-Mbit, both in 3V and in 1.8V versions – will also be moved from 120nm to 90nm technology in the coming months.

The NAND128 provides ultra-fast data throughput and erase capability. The Address lines and Data Input/Output signals of all members of the family are multiplexed onto an 8-bit bus, reducing pin count and allowing the use of a modular NAND interface, which enables manufacturers to produce variations of systems that use higher (or lower) density devices without changing the footprint.

A software tool chain available from ST allows fast product development, and can help extend the useful life of the memory chip. Tools include Error Correction Code (ECC) software; Bad Block Management (BBM) to recognize and replace a block that fails an Erase or Program operation, by copying its data to a valid block; Wear Leveling algorithms to optimize the aging of the device by distributing Erase and Program operations among all the blocks; File System OS Native reference software; and hardware simulation models.

The memory is organized into 1024 nominal 16 kbyte blocks, each of which is divided into pages of 512 bytes, plus 16 spare bytes per page, that can be read and programmed by page. The spare bytes are typically used for Error Correction Codes, software flags, or Bad Block identification. A Copy Back Program mode enables data stored in one page to be programmed directly into another without the need for external buffering, a feature typically used to move data if a Page Program operation fails due to a defective block. A Block Erase command is provided, with a block erase time of 2ms. Each block is specified for 100,000 Program and Erase cycles, and 10-year data retention.

The device has the ‘Chip Enable Don’t Care’ feature, which simplifies the microcontroller interface and streamlines the use of NAND Flash in combination with other types of memory such as NOR Flash and SRAM. A unique device ID can be factory programmed, and a User Programmable Serial number supports increased security in the target application.

The NAND128W3A2BN6E is available in volume now with pricing in the range of $4 to $4.5 in a lead-free TSOP48 package, and is characterized for the -40 to +85 degrees C temperature range.



Martes, 30 Agosto, 2005 - 01:01
powered by phppowered by MySQLPOWERED BY APACHEPOWERED BY CentOS© 2004 F.J.M.Información LegalPrensa
Esta web utiliza cookies, puedes ver nuestra política de cookies, aquí Si continuas navegando estás aceptándola
Política de cookies +