Caracteristicas tecnicas de 24C02

Features

•

Medium-voltage and Standard-voltage Operation

- 5.0 (V

= 4.5V to 5.5V)

- 2.7 (V

= 2.7V to 5.5V)

•

Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),
1024 x 8 (8K) or 2048 x 8 (16K)

•

Two-wire Serial Interface

•

Schmitt Trigger, Filtered Inputs for Noise Suppression

•

Bi-directional Data Transfer Protocol

•

100 kHz (2.7V) and 400 kHz (5V) Compatibility

•

Write Protect Pin for Hardware Data Protection

•

8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes

•

Partial Page Writes are Allowed

•

Self-timed Write Cycle (5 ms max)

•

High-reliability

- Endurance: 1 Million Write Cycles
- Data Retention: 100 Years

•

8-lead PDIP and 8-lead JEDEC SOIC Packages

Description

The AT24C01A/02/04/08/16 provides 1024/2048/4096/8192/16384 bits of serial elec-
trically erasable and programmable read-only memory (EEPROM) organized as
128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many
automotive applications where low-power and low-voltage operation are essential.
The AT24C01A/02/04/08/16 is available in space-saving 8-lead PDIP and 8-lead
JEDEC SOIC packages and is accessed via a two-wire serial interface. In addition,
the entire family is available in 5.0V (4.5V to 5.5V) and 2.7V (2.7V to 5.5V) versions.

Table 1. Pin Configuration

Pin Name

Function

A0 - A2

Address Inputs

SDA

Serial Data

SCL

Serial Clock Input

Write Protect

No Connect

Two-wire
Automotive
Serial EEPROM

1K (128 x 8)

2K (256 x 8)

4K (512 x 8)

8K (1024 x 8)

16K (2048 x 8)

AT24C01A
AT24C02
AT24C04
AT24C0

AT24C1

3256F-SEEPR-10/04

Note: 1. This device is not recom-

mended for new designs.
Please refer to AT24C08A.

2. This device is not recom-

mended for new designs.
Please refer to AT24C16A.

GND

VCC

SCL

SDA

8-lead PDIP

8-lead SOIC

GND

VCC

SCL

SDA

AT24C01A/02/04/08/16

3256F-SEEPR-10/04

Figure 1. Block Diagram

Pin Description

SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.

SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open-
collector devices.

DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device
address inputs that are hard wired for the AT24C01A and the AT24C02. As many as
eight 1K/2K devices may be addressed on a single bus system (device addressing is
discussed in detail under the Device Addressing section).

The AT24C04 uses the A2 and A1 inputs for hard wire addressing and a total of four 4K
devices may be addressed on a single bus system. The A0 pin is a no connect.

Absolute Maximum Ratings

Operating Temperature

......................................-55 °C to +125 °C

*NOTICE:

Stresses beyond those listed under †œAbsolute
Maximum Ratings† may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

Storage Temperature

.........................................-65 °C to +150 °C

Voltage on Any Pin
with Respect to Ground

........................................ -1.0V to +7.0V

Maximum Operating Voltage .......................................... 6.25V

DC Output Current........................................................ 5.0 mA

AT24C01A/02/04/08/16

3256F-SEEPR-10/04

The AT24C08 only uses the A2 input for hardwire addressing and a total of two 8K
devices may be addressed on a single bus system. The A0 and A1 pins are no
connects.

The AT24C16 does not use the device address pins, which limits the number of devices
on a single bus to one. The A0, A1 and A2 pins are no connects.

WRITE PROTECT (WP): The AT24C01A/02/04/16 has a Write Protect pin that provides
hardware data protection. The Write Protect pin allows normal read/write operations
when connected to ground (GND). When the Write Protect pin is connected to V

, the

write protection feature is enabled and operates as shown see Table 2.

Table 2. Write Protect

Notes:

1. This device is not recommended for new designs. Please refer to AT24C08A.
2. This device is not recommended for new designs. Please refer to AT24C16A.

Memory Organization

AT24C01A, 1K SERIAL EEPROM: Internally organized with 16 pages of 8 bytes each,
the 1K requires a 7-bit data word address for random word addressing.

AT24C02, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each,
the 2K requires an 8-bit data word address for random word addressing.

AT24C04, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each,
the 4K requires a 9-bit data word address for random word addressing.

AT24C08, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each,
the 8K requires a 10-bit data word address for random word addressing.

AT24C16, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes
each, the 16K requires an 11-bit data word address for random word addressing.

WP Pin
Status

Part of the Array Protected

24C01A

24C02

24C04

24C08

24C1

At V

Full (1K)
Array

Full (2K)
Array

Full (4K)
Array

Normal
Read/
Write
Operation

Upper
Half
(8K)
Array

At GND

Normal Read/Write Operations

AT24C01A/02/04/08/16

3256F-SEEPR-10/04

Note:

1. This parameter is characterized and is not 100% tested.

Notes:

1. V

min and V

max are reference only and are not tested.

Table 3. Pin Capacitance

Applicable over recommended operating range from T

= 25

°C, f = 1.0 MHz, V

= +2.7V.

Symbol

Test Condition

Max

Units

Conditions

I/O

Input/Output Capacitance (SDA)

I/O

= 0V

Input Capacitance (A

, A

, SCL)

= 0V

Table 4. DC Characteristics
Applicable over recommended operating range from: T

°C to +125 °C, V

= +2.7V to +5.5V (unless otherwise

noted).

Symbol

Parameter

Test Condition

Min

Typ

Max

Units

CC1

Supply Voltage

2.7

5.5

CC2

Supply Voltage

4.5

5.5

Supply Current V

= 5.0V

READ at 100 kHz

0.4

1.0

Supply Current V

= 5.0V

WRITE at 100 kHz

2.0

3.0

SB1

Standby Current V

= 2.7V

= V

or V

1.6

4.0

µA

SB2

Standby Current V

= 5.0V

= V

or V

8.0

18.0

µA

Input Leakage Current

= V

or V

0.10

3.0

µA

Output Leakage Current

OUT

= V

or V

0.05

3.0

µA

Input Low Leve

-0.6

x 0.3

Input High Level

x 0.7

+ 0.5

OL2

Output Low Level V

= 3.0V

= 2.1 mA

0.4

OL1

Output Low Level V

= 1.8V

= 0.15 mA

0.2

AT24C01A/02/04/08/16

3256F-SEEPR-10/04

Notes:

1. The AT24C01A/02/04/08 bearing the process letter †œD† on the package (the mark is located in the lower right corner on the

topside of the package), guarantees 400 kHz (2.5V, 2.7V).

2. This parameter is characterized and is not 100% tested (T

= 25

°C).

3. This parameter is characterized and is not 100% tested.

Device Operation

CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-
nal device. Data on the SDA pin may change only during SCL low time periods (see
. Data changes during SCL high periods will indicate a start or stop
condition as defined below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (see.

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (see ).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has
received each word. This happens during the ninth clock cycle.

Table 5. AC Characteristics
Applicable over recommended operating range from T

°C to +125 °C, V

= +2.7V to +5.5V, CL = 1 TTL Gate and

100 pF (unless otherwise noted).

Symbol

Parameter

AT24C01A/02/04/08,

2.7V

AT24C16, 2.7V

AT24C01A/02/04/08/16,

5.0V

Units

Min

Max

Min

Max

Min

Max

SCL

Clock Frequency, SCL

400

(1)

400

kHz

LOW

Clock Pulse Width Low

1.2

µs

HIGH

Clock Pulse Width High

0.6

µs

Noise Suppression Time

Clock Low to Data Out Valid

0.1

0.9

0.1

0.9

0.1

0.9

µs

BUF

Time the bus must be free before
a new transmission can star

1.2

µs

HD.STA

Start Hold Time

0.6

µs

SU.STA

Start Set-up Time

0.6

µs

HD.DAT

Data In Hold Time

µs

SU.DAT

Data In Set-up Time

100

Inputs Rise Tim

300

Inputs Fall Tim

300

SU.STO

Stop Set-up Time

0.6

µs

Data Out Hold Time

Write Cycle Time

Endurance

5.0V, 25

°C

Write

Cycles

AT24C01A/02/04/08/16

3256F-SEEPR-10/04

STANDBY MODE: The AT24C01A/02/04/08/16 features a low-power standby mode
which is enabled: (a) upon power-up and (b) after the receipt of the Stop bit and the
completion of any internal operations.

MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-
wire part can be reset by following these steps:

Clock up to 9 cycles.

Look for SDA high in each cycle while SCL is high.

Create a start condition.

Bus Timing

Figure 2. SCL: Serial Clock, SDA: Serial Data I/O

Write Cycle Timing

Figure 3. SCL: Serial Clock, SDA: Serial Data I/O

Note:

1. The write cycle time t

is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.

twr

(1)

STOP

CONDITION

START

CONDITION

WORDn

ACK

8th BIT

SCL

SDA

AT24C01A/02/04/08/16

3256F-SEEPR-10/04

Device Addressing

The 1K, 2K, 4K, 8K and 16K EEPROM devices all require an 8-bit device address word
following a start condition to enable the chip for a read or write operation (s).

The device address word consists of a mandatory one, zero sequence for the first four
most significant bits as shown. This is common to all the EEPROM devices.

The next 3 bits are the A2, A1 and A0 device address bits for the 1K/2K EEPROM.
These 3 bits must compare to their corresponding hard-wired input pins.

The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a
memory page address bit. The two device address bits must compare to their corre-
sponding hard-wired input pins. The A0 pin is no connect.

The 8K EEPROM only uses the A2 device address bit with the next 2 bits being for
memory page addressing. The A2 bit must compare to its corresponding hard-wired
input pin. The A1 and A0 pins are no connect.

The 16K does not use any device address bits but instead the 3 bits are used for mem-
ory page addressing. These page addressing bits on the 4K, 8K and 16K devices
should be considered the most significant bits of the data word address which follows.
The A0, A1 and A2 pins are no connect.

The eighth bit of the device address is the read/write operation select bit. A read opera-
tion is initiated if this bit is high and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will output a zero. If a compare is
not made, the chip will return to a standby state.

Write Operations

BYTE WRITE: A write operation requires an 8-bit data word address following the
device address word and acknowledgment. Upon receipt of this address, the EEPROM
will again respond with a zero and then clock in the first 8-bit data word. Following
receipt of the 8-bit data word, the EEPROM will output a zero and the addressing
device, such as a microcontroller, must terminate the write sequence with a stop condi-
tion. At this time the EEPROM enters an internally timed write cycle, t

, to the

nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will
not respond until the write is complete (see.

PAGE WRITE: The 1K/2K EEPROM is capable of an 8-byte page write, and the 4K, 8K
and 16K devices are capable of 16-byte page writes.

A page write is initiated the same as a byte write, but the microcontroller does not send
a stop condition after the first data word is clocked in. Instead, after the EEPROM
acknowledges receipt of the first data word, the microcontroller can transmit up to seven
(1K/2K) or fifteen (4K, 8K, 16K) more data words. The EEPROM will respond with a zero
after each data word received. The microcontroller must terminate the page write
sequence with a stop condition (see).

The data word address lower three (1K/2K) or four (4K, 8K, 16K) bits are internally
incremented following the receipt of each data word. The higher data word address bits
are not incremented, retaining the memory page row location. When the word address,
internally generated, reaches the page boundary, the following byte is placed at the
beginning of the same page. If more than eight (1K/2K) or sixteen (4K, 8K, 16K) data
words are transmitted to the EEPROM, the data word address will †œroll over† and previ-
ous data will be overwritten.

ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send-

AT24C01A/02/04/08/16

3256F-SEEPR-10/04

ing a start condition followed by the device address word. The read/write bit is
representative of the operation desired. Only if the internal write cycle has completed
will the EEPROM respond with a zero allowing the read or write sequence to continue.

Read Operations

Read operations are initiated the same way as write operations with the exception that
the read/write select bit in the device address word is set to one. There are three read
operations: current address read, random address read and sequential read.

CURRENT ADDRESS READ: The internal data word address counter maintains the
last address accessed during the last read or write operation, incremented by one. This
address stays valid between operations as long as the chip power is maintained. The
address †œroll over† during read is from the last byte of the last memory page to the first
byte of the first page. The address †œroll over† during write is from the last byte of the cur-
rent page to the first byte of the same page.

Once the device address with the read/write select bit set to one is clocked in and
acknowledged by the EEPROM, the current address data word is serially clocked out.
The microcontroller does not respond with an input zero but does generate a following
stop condition (see).

RANDOM READ: A random read requires a †œdummy† byte write sequence to load in the
data word address. Once the device address word and data word address are clocked
in and acknowledged by the EEPROM, the microcontroller must generate another start
condition. The microcontroller now initiates a current address read by sending a device
address with the read/write select bit high. The EEPROM acknowledges the device
address and serially clocks out the data word. The microcontroller does not respond
with a zero but does generate a following stop condition (see.

SEQUENTIAL READ: Sequential reads are initiated by either a current address read or
a random address read. After the microcontroller receives a data word, it responds with
an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to
increment the data word address and serially clock out sequential data words. When the
memory address limit is reached, the data word address will †œroll over† and the sequen-
tial read will continue. The sequential read operation is terminated when the
microcontroller does not respond with a zero but does generate a following stop condi-
tion (s.

Figure 7. Device Address

AT24C01A/02/04/08/16

3256F-SEEPR-10/04

AT24C01A Ordering Information

Ordering Code

Package

Operation Range

AT24C01A-10PA-5.0C

AT24C01A-10SA-5.0C

8P3

8S1

Automotive

(

-40 °C to 125 °C)

AT24C01A-10PA-2.7C

AT24C01A-10SA-2.7C

8P3

8S1

Automotive

(

-40 °C to 125 °C)

Package Type

8P3

8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

8S1

8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

Options

-5.0

Standard Operation (4.5V to 5.5V)

-2.7

Low-voltage (2.7V to 5.5V)

AT24C01A/02/04/08/16

3256F-SEEPR-10/04

Note:

1. This device is not recommended for new designs. Please refer to AT24C08A.

AT24C08

rdering Information

Ordering Code

Package

Operation Range

AT24C08-10PA-5.0C

AT24C08N-10SA-5.0C

8P3

8S1

Automotive

(

-40 °C to 125 °C)

AT24C08-10PA-2.7C

AT24C08N-10SA-2.7C

8P3

8S1

Automotive

(

-40 °C to 125 °C)

Package Type

8P3

8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

8S1

8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

Options

-5.0

Standard Operation (4.5V to 5.5V)

-2.7

Low-voltage (2.7V to 5.5V)

AT24C01A/02/04/08/16

3256F-SEEPR-10/04

Note:

1. This device is not recommended for new designs. Please refer to AT24C16A.

AT24C16

rdering Information

Ordering Code

Package

Operation Range

AT24C16-10PA-5.0C

AT24C16N-10SA-5.0C

8P3

8S1

Automotive

(

-40 °C to 125 °C)

AT24C16-10PA-2.7C

AT24C16N-10SA-2.7C

8P3

8S1

Automotive

(

-40 °C to 125 °C)

Package Type

8P3

8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

8S1

8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

Options

-5.0

Standard Operation (4.5V to 5.5V)

-2.7

Low-voltage (2.7V to 5.5V)

AT24C01A/02/04/08/16

3256F-SEEPR-10/04

Packaging Information

8P3 - PDIP

2325 Orchard Parkway
San Jose, CA 95131

TITLE

DRAWING NO.

REV.

8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)

01/09/02

8P3

Notes: 1.

This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information.

Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.

3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.

and eA measured with the leads constrained to be perpendicular to datum.

5. Pointed or rounded lead tips are preferred to ease insertion.

b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).

COMMON DIMENSIONS

(Unit of Measure = inches)

SYMBOL

MIN

NOM

MAX

NOTE

A2 A

4 PLCS

0.210

A2 0.115

0.130 0.195

b 0.014

0.018 0.022 5

b2 0.045

0.060

0.070

b3 0.030 0.039 0.045 6

c 0.008 0.010 0.014

D 0.355 0.365 0.400 3

D1 0.005 -

E 0.300 0.310 0.325 4

E1 0.240

0.250

0.280

0.100

BSC

0.300 BSC

L 0.115

0.130 0.150 2

Top View

Side View

End View

AT24C01A/02/04/08/16

3256F-SEEPR-10/04

8S1 - JEDEC SOIC

2325 Orchard Parkway
San Jose, CA 95131

TITLE

DRAWING NO.

REV.

8S2, 8-lead, 0.209" Body, Plastic Small
Outline Package (EIAJ)

10/7/03

8S2

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL

MIN

NOM

MAX

NOTE

Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
2.

Mismatch of the upper and lower dies and resin burrs are not included.

3. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded.

Determines the true geometric position.

Values b and C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/

-0.005 mm.

A 1.70

2.16

A1 0.05

0.25

b 0.35

0.48

C 0.15

0.35 5

D 5.13

5.35

E1 5.18

5.40 2,

E 7.70

8.26

L 0.51

0.85

•ˆ…

0 °

8 °

1.27 BSC

End View

Side View

•ˆ…

Top View

Printed on recycled paper.

3256F-SEEPR-10/04

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