1

Features

•

Low-Voltage and Standard-Voltage Operation

- 2.7 (V

CC

 = 2.7V to 5.5V)

- 1.8 (V

CC

 = 1.8V to 5.5V)

•

Low-Power Devices (I

SB

 = 2

 

µA at 5.5V) Available

•

Internally Organized 4096 x 8, 8192 x 8

•

2-Wire Serial Interface

•

Schmitt Trigger, Filtered Inputs for Noise Suppression

•

Bidirectional Data Transfer Protocol 

•

100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Clock Rate

•

Write Protect Pin for Hardware Data Protection

•

32-Byte Page Write Mode (Partial Page Writes Allowed)

•

Self-Timed Write Cycle (10 ms max)

•

High Reliability

- Endurance: 1 Million Write Cycles 
- Data Retention: 100 Years

•

Automotive Grade and Extended Temperature Devices Available

•

8-Pin JEDEC PDIP, 8-Pin JEDEC SOIC, 8-Pin EIAJ SOIC, 
and 8-pin TSSOP Packages

Description

The AT24C32/64 provides 32,768/65,536 bits of serial electrically erasable and pro-
grammable read only memory (EEPROM) organized as 4096/8192 words of 8 bits
each. The device’s cascadable feature allows up to 8 devices to share a common 2-
wire bus. The device is optimized for use in many industrial and commercial applica-
tions where low power and low voltage operation are essential. The AT24C32/64 is
available in space saving 8-pin JEDEC PDIP, 8-pin JEDEC SOIC, 8-pin EIAJ SOIC,
and 8-pin TSSOP (AT24C64) packages and is accessed via a 2-wire serial interface.
In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V)
versions.

2-Wire
Serial EEPROM

32K (4096 x 8)

64K (8192 x 8)

AT24C32
AT24C64

Rev. 0336K-SEEPR-7/03

2-Wire, 32K 
Serial E

2

PROM

Pin Configurations

Pin Name

Function

A0 - A2

Address Inputs

SDA

Serial Data

SCL

Serial Clock Input

WP

Write Protect

8-Pin PDIP

1

2

3

4

8

7

6

5

A0

A1

A2

GND

VCC

WP

SCL

SDA

8-Pin SOIC

1

2

3

4

8

7

6

5

A0

A1

A2

GND

VCC

WP

SCL

SDA

8-Pin TSSOP

1

2

3

4

8

7

6

5

A0

A1

A2

GND

VCC

WP

SCL

SDA

2

AT24C32/64

0336K-SEEPR-7/03

Block Diagram  

Absolute Maximum Ratings*

Operating Temperature .................................. -55

°

C to +125

°

C

*NOTICE:

Stresses beyond those listed under †œAbsolute 
Maximum Ratings†� may cause permanent dam-
age to the device. This is a stress rating only and 
functional operation of the device at these or any 
other conditions beyond those indicated in the 
operational sections of this specification is not 
implied. Exposure to absolute maximum rating 
conditions for extended periods may affect 
device reliability.

Storage Temperature ..................................... -65

°

C to +150

°

C

Voltage on Any Pin
with Respect to Ground .....................................-1.0V to +7.0V

Maximum Operating Voltage .......................................... 6.25V

DC Output Current........................................................ 5.0 mA

3

AT24C32/64

0336K-SEEPR-7/03

Pin Description

SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.

SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open
collector devices.

DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address
inputs that are hard wired or left not connected for hardware compatibility with
AT24C16. When the pins are hardwired, as many as eight 32K/64K devices may be
addressed on a single bus system (device addressing is discussed in detail under the
Device Addressing section). When the pins are not hardwired, the default A

2

, A

1

, and A

0

are zero.

WRITE PROTECT (WP): The write protect input, when tied to GND, allows normal write
operations. When WP is tied high to V

CC

, all write operations to the upper quandrant

(8/16K bits) of memory are inhibited. If left unconnected, WP is internally pulled down to
GND.

Memory Organization

AT24C32/64, 32K/64K SERIAL EEPROM: The 32K/64K is internally organized as 256
pages of 32 bytes each. Random word addressing requires a 12/13 bit data word
address.

4

AT24C32/64

0336K-SEEPR-7/03

Note:

1. This parameter is characterized and is not 100% tested.

Note:

1. V

IL

 min and V

IH

 max are reference only and are not tested.

Pin Capacitanc

Applicable over recommended operating range from T

A 

= 25

°

C, f = 1.0 MHz, V

CC

 = +1.8V.

Symbol

Test Condition

Max

Units

Conditions

C

I/O

Input/Output Capacitance (SDA)

8

pF

V

I/O

 = 0V

C

IN

Input Capacitance (A

0

, A

1

, A

2

, SCL)

6

pF

V

IN

 = 0V

DC Characteristics

Applicable over recommended operating range from: T

AI

 = -40

°

C to +85

°

C, V

CC

 = +1.8V to +5.5V, T

AC

 = 0

°

C to +70

°

C,

V

CC

 = +1.8V to +5.5V (unless otherwise noted).

Symbol

Parameter

Test Condition

Min

Typ

Max

Units

V

CC1

Supply Voltage

1.8

5.5

V

V

CC2

Supply Voltage

2.5

5.5

V

V

CC3

Supply Voltage

2.7

5.5

V

V

CC4

Supply Voltage

4.5

5.5

V

I

CC1

Supply Current 

V

CC

 = 5.0V

READ at 100 kHz

0.4

1.0

mA

I

CC2

Supply Current 

V

CC

 = 5.0V

WRITE at 100 kHz

2.0

3.0

mA

I

SB1

Standby Current

           (1.8V option)

V

CC

 = 1.8V

V

IN

 = V

CC

 or V

SS

0.1

µ

A

V

CC

 = 5.5V

2.0

I

SB2

Standby Current

           (2.5V option)

V

CC

 = 2.5V

V

IN

 = V

CC

 or V

SS

0.5

µ

A

V

CC

 = 5.5V

2.0

I

SB3

Standby Current

           (2.7V option)

V

CC

 = 2.7V

V

IN

 = V

CC

 or V

SS

0.5

µ

A

V

CC

 = 5.5V

2.0

I

SB4

Standby Current

           (5V option)

V

CC

 = 4.5 - 5.5V

V

IN

 = V

CC

 or V

SS

20

35

µ

A

I

LI

Input Leakage 
Current

V

IN

 = V

CC 

or

 

V

SS

0.10

3.0

µ

A

I

LO

Output Leakage 
Current

V

OUT

 = V

CC 

or

 

V

SS

0.05

3.0

µ

A

V

IL

Input Low Leve

-0.6

V

CC

 x 0.3

V

V

IH

Input High Level

V

CC

 x 0.7

V

CC

 + 0.5

V

V

OL2

Output Low Level 

V

CC

 = 3.0V

I

OL

 = 2.1 mA

0.4

V

V

OL1

Output Low Level 

V

CC

 = 1.8V

I

OL

 = 0.15 mA

0.2

V

5

AT24C32/64

0336K-SEEPR-7/03

Note:

1. This parameter is characterized and is not 100% tested.

AC Characteristics

Applicable over recommended operating range from T

A 

= -40

°

C to +85

°

C, V

CC

 = +1.8V to +5.5V, CL = 1 TTL Gate and 100

pF (unless otherwise noted).

Symbol

Parameter

1.8-volt

 2.7-, 2.5-volt

5.0-volt

Units

Min

Max

Min

Max

Min

Max

f

SCL

Clock Frequency, SCL

100

100

400

kHz

t

LOW

Clock Pulse Width Low

4.7

4.7

1.2

µ

s

t

HIGH

Clock Pulse Width High

4.0

4.0

0.6

µ

s

t

I

Noise Suppression Time

100

100

50

ns

t

AA

Clock Low to Data Out Valid

0.1

4.5

0.1

4.5

0.1

0.9

µ

s

t

BUF

Time the bus must be free 
before a new transmission can start

4.7

4.7

1.2

µ

s

t

HD.STA

Start Hold Time

4.0

4.0

0.6

µ

s

t

SU.STA

Start Set-up Time

4.7

4.7

0.6

µ

s

t

HD.DAT

Data In Hold Time

0

0

0

µ

s

t

SU.DAT

Data In Set-up Time

200

200

100

ns

t

R

Inputs Rise Tim

1.0

1.0

0.3

µ

s

t

F

Inputs Fall Time

300

300

300

ns

t

SU.STO

Stop Set-up Time

4.7

4.7

0.6

µ

s

t

DH

Data Out Hold Time

100

100

50

ns

t

WR

Write Cycle Time

20

10

10

ms

Endur

5.0V, 25

°

C, Page Mode

1M

1M

1M

Write 

Cycles

6

AT24C32/64

0336K-SEEPR-7/03

Device Operation

CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-
nal device. Data on the SDA pin may change only during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL high periods will indicate a start
or stop condition as defined below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (refer to Start and Stop Definition timing
diagram).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (refer to Start and Stop Definition timing diagram).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to
acknowledge that it has received each word.

STANDBY MODE: The AT24C32/64 features a low power standby mode which is
enabled: a) upon power-up and b) after the receipt of the STOP bit and the completion
of any internal operations.

MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-
wire part can be reset by following these steps:

(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then
(c) create a start condition as SDA is high.

7

AT24C32/64

0336K-SEEPR-7/03

Bus Timing
SCL: Serial Clock, SDA: Serial Data I/O  

Write Cycle Timing
SCL: Serial Clock, SDA: Serial Data I/O  

Note:

1. The write cycle time t

WR

 is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.

twr

(1)

STOP

CONDITION

START

CONDITION

WORDn

ACK

8th BIT

SCL

SDA

8

AT24C32/64

0336K-SEEPR-7/03

Data Validity  

Start and Stop Definition  

Output Acknowledge  

9

AT24C32/64

0336K-SEEPR-7/03

Device Addressing

The 32K/64K EEPROM requires an 8-bit device address word following a start condition
to enable the chip for a read or write operation (refer to. The device address
word consists of a mandatory one, zero sequence for the first four most significant bits
as shown. This is common to all 2-wire EEPROM devices.

The 32K/64K uses the three device address bits A2, A1, A0 to allow as many as eight
devices on the same bus. These bits must compare to their corresponding hardwired
input pins. The A2, A1, and A0 pins use an internal proprietary circuit that biases them
to a logic low condition if the pins are allowed to float.

The eighth bit of the device address is the read/write operation select bit. A read opera-
tion is initiated if this bit is high and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will output a zero. If a compare is
not made, the device will return to standby state.

NOISE PROTECTION: Special internal circuitry placed on the SDA and SCL pins pre-
vent small noise spikes from activating the device. A low-V

CC

 detector (5-volt option)

resets the device to prevent data corruption in a noisy environment.

DATA SECURITY: The AT24C32/64 has a hardware data protection scheme that allows
the user to write protect the upper quadrant (8/16K bits) of memory when the WP pin is
at V

CC

.

Write Operations

BYTE WRITE: A write operation requires two 8-bit data word addresses following the
device address word and acknowledgment. Upon receipt of this address, the EEPROM
will again respond with a zero and then clock in the first 8-bit data word. Following
receipt of the 8-bit data word, the EEPROM will output a zero and the addressing
device, such as a microcontroller, must terminate the write sequence with a stop condi-
tion. At this time the EEPROM enters an internally-timed write cycle, t

WR

, to the

nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will
not respond until the write is complete (refer to

PAGE WRITE: The 32K/64K EEPROM is capable of 32-byte page writes.

A page write is initiated the same way as a byte write, but the microcontroller does not
send a stop condition after the first data word is clocked in. Instead, after the EEPROM
acknowledges receipt of the first data word, the microcontroller can transmit up to 31
more data words. The EEPROM will respond with a zero after each data word received.
The microcontroller must terminate the page write sequence with a stop condition (refer
to.

The data word address lower 5 bits are internally incremented following the receipt of
each data word. The higher data word address bits are not incremented, retaining the
memory page row location. When the word address, internally generated, reaches the
page boundary, the following byte is placed at the beginning of the same page. If more
than 32 data words are transmitted to the EEPROM, the data word address will †œroll
over†� and previous data will be overwritten.

ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send-
ing a start condition followed by the device address word. The read/write bit is
representative of the operation desired. Only if the internal write cycle has completed
will the EEPROM respond with a zero, allowing the read or write sequence to continue.

10

AT24C32/64

0336K-SEEPR-7/03

Read 
Operations

Read operations are initiated the same way as write operations with the exception that the
read/write select bit in the device address word is set to one. There are three read operations:
current address read, random address read and sequential read.

CURRENT ADDRESS READ: The internal data word address counter maintains the last
address accessed during the last read or write operation, incremented by one. This address
stays valid between operations as long as the chip power is maintained. The address †œroll
over†� during read is from the last byte of the last memory page, to the first byte of the first
page. The address †œroll over†� during write is from the last byte of the current page to the first
byte of the same page.

Once the device address with the read/write select bit set to one is clocked in and acknowl-
edged  by the EEPROM,  the current address data  word is serially clocked out. The
microcontroller does not respond with an input zero but does generate a following stop condi-
tion (refer to).

RANDOM READ: A random read requires a †œdummy†� byte write sequence to load in the data
word address. Once the device address word and data word address are clocked in and
acknowledged by the EEPROM, the microcontroller must generate another start condition.
The microcontroller now initiates a current address read by sending a device address with the
read/write select bit high. The EEPROM acknowledges the device address and serially clocks
out the data word. The microcontroller does not respond with a zero but does generate a fol-
lowing stop condition (refer to.

SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a ran-
dom address read. After the microcontroller receives a data word, it responds with an
acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment
the data word address and serially clock out sequential data words. When the memory
address limit is reached, the data word address will †œroll over†� and the sequential read will con-
tinue. The sequential read operation is terminated when the microcontroller does not respond
with a zero but does generate a following stop condition (refer to 

11

AT24C32/64

0336K-SEEPR-7/03

Figure 1.  Device Address  

Figure 2.  Byte Write  

Figure 3.  Page Write  

Note:

1. * = DON’T CARE bits

2. †  = DON’T CARE bits for the 32K

12

AT24C32/64

0336K-SEEPR-7/03

Figure 4.  Current Address Read  

Figure 5.  Random Read  

Note:

1. * = DON’T CARE bits

Figure 6.  Sequential Read  

13

AT24C32/64

0336K-SEEPR-7/03

 

Note:

For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics tables.

AT24C32 Ordering Information

Ordering Code

Package

Operation Range

AT24C32-10PI-2.7

AT24C32N-10SI-2.7

AT24C32W-10SI-2.7

8P3

8S1

8S2

Industrial

(-40

°

C to 85

°

C)

AT24C32-10PI-1.8

AT24C32N-10SI-1.8

AT24C32W-10SI-1.8

8P3

8S1

8S2

Industrial

(-40

°

C to 85

°

C)

Package Type

8P3

8-lead, 0.300†� Wide, Plastic Dual Inline Package (PDIP)

8S1

8-lead, 0.150†� Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

8S2

8-lead, 0.200†� Wide, Plastic Gull Wing Small Outline (EIAJ SOIC)

Options

-2.7

Low Voltage (2.7V to 5.5V)

-1.8

Low Voltage (1.8V to 5.5V)

14

AT24C32/64

0336K-SEEPR-7/03

 

Note:

For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics tables.

AT24C64 Ordering Information

Ordering Code

Package

Operation Range

AT24C64-10PI-2.7

AT24C64N-10SI-2.7

AT24C64W-10SI-2.7

AT24C64-10TI-2.7

8P3

8S1

8S2

8A2

Industrial

(-40

°

C to 85

°

C)

AT24C64-10PI-1.8

AT24C64N-10SI-1.8

AT24C64W-10SI-1.8

AT24C64-10TI-1.8

8P3

8S1

8S2

8A2

Industrial

(-40

°

C to 85

°

C)

Package Type

8P3

8-lead, 0.300†� Wide, Plastic Dual Inline Package (PDIP)

8S1

8-lead, 0.150†� Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

8S2

8-lead, 0.200†� Wide, Plastic Gull Wing Small Outline (EIAJ SOIC)

8A2

8-lead, 0.170†� Wide, Thin Shrink Small Outline Package (TSSOP)

Options

-2.7

Low Voltage (2.7V to 5.5V)

-1.8

Low Voltage (1.8V to 5.5V)

15

AT24C32/64

0336K-SEEPR-7/03

Packaging Information

8P3 - PDIP  

2325 Orchard Parkway
San Jose, CA  95131

TITLE

DRAWING NO.

R

REV.  

8P3, 8-lead, 0.300" Wide Body, Plastic Dual 
In-line Package (PDIP)

01/09/02

8P3

B

D

D1

E

E1

e

L

b2

b

A2 A

1

N

eA

c

b3

4 PLCS

Top View

Side View

End View

COMMON DIMENSIONS

(Unit of Measure = inches)

SYMBOL

MIN

NOM

MAX

NOTE

Notes:

1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions.  Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions.  Dambar protrusions shall not exceed 0.010 (0.25 mm).

A

0.210

2

A2

0.115

0.130

0.195

b

0.014

0.018

0.022

5

b2

0.045

0.060

0.070

6

b3

0.030

0.039

0.045

6

c

0.008

0.010

0.014

D

0.355

0.365

0.400

3

D1

0.005

3

E

0.300

0.310

0.325

4

E1

0.240

0.250

0.280

3

e

0.100 BSC

eA

0.300 BSC

4

L

0.115

0.130

0.150

2

16

AT24C32/64

0336K-SEEPR-7/03

8S1 - JEDEC SOIC  

  2325 Orchard Parkway
  San Jose, CA  95131

TITLE

DRAWING NO.

R

REV.  

Note:

10/10/01

8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing 
Small Outline (JEDEC SOIC)

8S1

A

H

1

2

N

3

Top View

C

E

End View

A

B

L

A2

e

D

Side View

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL

MIN

NOM

MAX

NOTE

 

This drawing is for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc.

A

-

-

1.75

B

-

-

0.51

C

-

-

0.25

D

-

-

5.00

E

-

-

4.00

e

1.27 BSC

H

-

-

6.20

L

-

-

1.27

17

AT24C32/64

0336K-SEEPR-7/03

8S2 - EIAJ SOIC  

2325 Orchard Parkway
San Jose, CA  95131

TITLE

DRAWING NO.

R

REV.  

8S2, 8-lead, 0.209" Body, Plastic Small 
Outline Package (EIAJ)

5/2/02

8S2

B

Top View

Side View

End View

H

1

N

C

E

A

b

L

A1

e

D

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL

MIN

NOM

MAX

NOTE

Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.

2. Mismatch of the upper and lower dies and resin burrs aren't included.
3. It is recommended that upper and lower cavities be equal.  If they are different, the larger dimension shall be regarded.
4. Determines the true geometric position.
5. Values b,C apply to pb/Sn solder plated terminal.  The standard thickness of the solder layer shall be 0.010 +0.010/-0.005 mm.

A

1.78

2.03

A1

0.05

0.33

b

0.35

0.51

5

C

0.18

0.25

5

D

5.13

5.38

E

5.13

5.41

2, 3

H

7.62

8.38

L

0.51

0.89

e

           1.27 BSC

4

18

AT24C32/64

0336K-SEEPR-7/03

8A2 - TSSOP  

2325 Orchard Parkway
San Jose, CA  95131

TITLE

DRAWING NO.

R

REV.  

5/30/02

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL

MIN

NOM

MAX

NOTE

D

2.90

3.00

3.10

2, 5

E

6.40 BSC

E1

4.30

4.40

4.50

3, 5

A

-

-

1.20

A2

0.80

1.00

1.05

b

0.19

-

0.30

4

e

0.65 BSC

L

0.45

0.60

0.75

L1

1.00 REF

8A2, 8-lead, 4.4 mm Body, Plastic 
Thin Shrink Small Outline Package (TSSOP)

Notes:

1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, 

datums, etc.

2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 

0.15 mm (0.006 in) per side.

3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm 

(0.010 in) per side.

4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the 

b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between 
protrusion and adjacent lead is 0.07 mm. 

5. Dimension D and E1 to be determined at Datum Plane H.

8A2

B

Side View

End View

Top View

A2

A

L

L1

D

1

2

3

E1

N

b

Pin 1 indicator

this corner

E

e

 Printed on recycled paper.

0336K-SEEPR-7/03

xM

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