Caracteristicas tecnicas de ICL8038

File Number 2864.4

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

Intersil and Design is a trademark of Intersil Americas Inc.

ICL8038

Precision Waveform Generator/Voltage

Controlled Oscillator

The ICL8038 waveform generator is a monolithic integrated
circuit capable of producing high accuracy sine, square,
triangular, sawtooth and pulse waveforms with a minimum of
external components. The frequency (or repetition rate) can
be selected externally from 0.001Hz to more than 300kHz
using either resistors or capacitors, and frequency
modulation and sweeping can be accomplished with an
external voltage. The ICL8038 is fabricated with advanced
monolithic technology, using Schottky barrier diodes and
thin film resistors, and the output is stable over a wide range
of temperature and supply variations. These devices may be
interfaced with phase locked loop circuitry to reduce
temperature drift to less than 250ppm/

Features

• Low Frequency Drift with Temperature . . . . . 250ppm/

• Low Distortion . . . . . . . . . . . . . . . 1% (Sine Wave Output)

• High Linearity . . . . . . . . . . .0.1% (Triangle Wave Output)

• Wide Frequency Range . . . . . . . . . . . .0.001Hz to 300kHz

• Variable Duty Cycle . . . . . . . . . . . . . . . . . . . . . 2% to 98%

• High Level Outputs. . . . . . . . . . . . . . . . . . . . . . TTL to 28V

• Simultaneous Sine, Square, and Triangle Wave

Outputs

• Easy to Use - Just a Handful of External Components

Required

Pinout

ICL8038

(PDIP, CERDIP)

TOP VIEW

Functional Diagram

Ordering Information

PART NUMBER

STABILITY

TEMP. RANGE (

PACKAGE

PKG. NO.

ICL8038CCPD 250ppm/

C (Typ)

0 to 70

14 Ld PDIP

E14.3

ICL8038CCJD 250ppm/

C (Typ)

0 to 70

14 Ld CERDIP

F14.3

ICL8038BCJD 180ppm/

C (Typ)

0 to 70

14 Ld CERDIP

F14.3

ICL8038ACJD 120ppm/

C (Typ)

0 to 70

14 Ld CERDIP

F14.3

SINE

TRIANGLE

DUTY CYCLE

V+

FM BIAS

SINE WAVE

V- OR GND

TIMING

SQUARE

FM SWEEP

ADJUST

CAPACITOR

WAVE OUT

INPUT

SINE WAVE

ADJUST

WAVE OUT

OUT

FREQUENCY

ADJUST

COMPARATOR

FLIP-FLOP

SINE

CONVERTER

BUFFER

V+

V- OR GND

CURRENT

SOURCE

CURRENT

SOURCE

Data Sheet

April 2001

[ /Title
(ICL80
38)
/Sub-
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(Preci-
sion
Wave-
form
Gener-
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ltage
Con-
trolled
Oscil-
lator)
/Autho
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/Key-
words
(Inter-
sil
Corpo-
ration,
semi-
con-
ductor,
wave-
form
genera-
tor,
volt-
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con-
trolled
oscilla-
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preci-
sion,

OBSOL

ETE PR

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NO REC

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PLACEM

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contact

our Tec

hnical S

upport C

enter at

1-888-IN

TERSIL

or www

.intersil

.com/ts

Absolute Maximum Ratings

Thermal Information

Supply Voltage (V- to V+) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36V
Input Voltage (Any Pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- to V+
Input Current (Pins 4 and 5). . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA
Output Sink Current (Pins 3 and 9) . . . . . . . . . . . . . . . . . . . . . 25mA

Operating Conditions

Temperature Range

ICL8038AC, ICL8038BC, ICL8038CC . . . . . . . . . . . . 0

C to 70

Thermal Resistance (Typical, Note 1)

(

C/W)

(

C/W)

CERDIP Package. . . . . . . . . . . . . . . . .

PDIP Package . . . . . . . . . . . . . . . . . . .

115

N/A

Maximum Junction Temperature (Ceramic Package) . . . . . . . .175

Maximum Junction Temperature (Plastic Package) . . . . . . . .150

Maximum Storage Temperature Range . . . . . . . . . -65

C to 150

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300

Die Characteristics

Back Side Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-

CAUTION: Stresses above those listed in †œAbsolute Maximum Ratings† may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

SUPPLY

±10V or +20V, T

= 25

C, R

= 10k

Ω, Test Circuit Unless Otherwise Specified

PARAMETER

SYMBOL

TEST

CONDITIONS

ICL8038CC

ICL8038BC

ICL8038AC

UNITS

MIN TYP MAX MIN TYP MAX MIN TYP MAX

Supply Voltage Operating Range

SUPPLY

V+

Single Suppl

+10

+30

+10

+30

+10

+30

V+, V-

Dual Supplies

±5

±15

±5

±15

±5

±15

Supply Current

SUPPLY

±10V

(Note 2)

FREQUENCY CHARACTERISTICS (All Waveforms)

Max. Frequency of Oscillation

MAX

100

kHz

Sweep Frequency of FM Input

SWEEP

kHz

Sweep FM Range

(Note 3)

35:1

FM Linearity

10:1 Ratio

0.5

0.2

Frequency Drift with
Temperature (Note 5)

Δf/ΔT

C to 70

250

180

120

ppm/

Frequency Drift with Supply Voltage

Δf/ΔV

Over Supply

Voltage Range

0.05

%/V

OUTPUT CHARACTERISTICS

Square Wave

Leakage Current

OLK

= 30V

μA

Saturation Voltage

SAT

SINK

= 2mA

0.2

0.5

0.2

0.4

0.2

0.4

Rise Time

= 4.7k

Ω

180

Fall Time

= 4.7k

Ω

Typical Duty Cycle Adjust
(Note 6)

ΔD

Triangle/Sawtooth/Ramp

Amplitude

TRIAN-

GLE

TRI

= 100k

Ω

0.30 0.33

SUPPLY

Linearity

0.1

0.05

Output Impedance

OUT

= 5mA

200

Ω

ICL8038

Sine Wave

Amplitude

SINE

= 100k

Ω

0.2

0.22

0.2

0.22

0.2

0.22

SUPPLY

THD

= 1M

Ω

(Note 4)

2.0

1.5

1.0

1.5

THD Adjusted

THD

Use Figure 4

1.5

1.0

0.8

NOTES:

2. R

and R

currents not included.

3. V

SUPPLY

= 20V; R

and R

= 10k

Ω, f •‰… 10kHz nominal; can be extended 1000 to 1. See Figures 5A and 5B.

4. 82k

Ω connected between pins 11 and 12, Triangle Duty Cycle set at 50%. (Use R

and R

5. Figure 1, pins 7 and 8 connected, V

SUPPLY

±10V. See Typical Curves for T.C. vs V

SUPPLY

6. Not tested, typical value for design purposes only.

Electrical Specifications

SUPPLY

±10V or +20V, T

= 25

C, R

= 10k

Ω, Test Circuit Unless Otherwise Specified (Continued)

PARAMETER

SYMBOL

TEST

CONDITIONS

ICL8038CC

ICL8038BC

ICL8038AC

UNITS

MIN TYP MAX MIN TYP MAX MIN TYP MAX

Test Conditions

PARAMETER

MEASURE

Supply Current

10k

Ω

10k

Ω

10k

Ω

3.3nF

Closed

Current Into Pin 6

Sweep FM Range (Note 7)

10k

Ω

10k

Ω

10k

Ω

3.3nF

Open

Frequency at Pin 9

Frequency Drift with Temperature

10k

Ω

10k

Ω

10k

Ω

3.3nF

Closed

Frequency at Pin 3

Frequency Drift with Supply Voltage (Note 8)

10k

Ω

10k

Ω

10k

Ω

3.3nF

Closed

Frequency at Pin 9

Output Amplitude (Note 10)

Sine

10k

Ω

10k

Ω

10k

Ω

3.3nF

Closed

Pk-Pk Output at Pin 2

Triangle

10k

Ω

10k

Ω

10k

Ω

3.3nF

Closed

Pk-Pk Output at Pin 3

Leakage Current (Off) (Note 9)

10k

Ω

10k

Ω

3.3nF

Closed

Current into Pin 9

Saturation Voltage (On) (Note 9)

10k

Ω

10k

Ω

3.3nF

Closed

Output (Low) at Pin 9

Rise and Fall Times (Note 11)

10k

Ω

10k

Ω

4.7k

Ω

3.3nF

Closed

Waveform at Pin 9

Duty Cycle Adjust (Note 11)

Max

50k

Ω

~1.6k

Ω

10k

Ω

3.3nF

Closed

Waveform at Pin 9

Min

~25k

Ω

50k

Ω

10k

Ω

3.3nF

Closed

Waveform at Pin 9

Triangle Waveform Linearity

10k

Ω

10k

Ω

10k

Ω

3.3nF

Closed

Waveform at Pin 3

Total Harmonic Distortion

10k

Ω

10k

Ω

10k

Ω

3.3nF

Closed

Waveform at Pin 2

NOTES:

7. The hi and lo frequencies can be obtained by connecting pin 8 to pin 7 (f

) and then connecting pin 8 to pin 6 (f

). Otherwise apply Sweep

Voltage at pin 8 (

SUPPLY

+2V)

≤ V

SWEEP

≤ V

SUPPLY

where V

SUPPLY

is the total supply voltage. In Figure 5B, pin 8 should vary between

5.3V and 10V with respect to ground.

8. 10V

≤ V+ ≤ 30V, or ±5V ≤ V

SUPPLY

≤ ±15V.

9. Oscillation can be halted by forcing pin 10 to +5V or -5V.

10. Output Amplitude is tested under static conditions by forcing pin 10 to 5V then to -5V.
11. Not tested; for design purposes only.

ICL8038

Test Circuit

Application Information

(See Functional Diagram)

An external capacitor C is charged and discharged by two
current sources. Current source #2 is switched on and off by a
flip-flop, while current source #1 is on continuously. Assuming
that the flip-flop is in a state such that current source #2 is off,
and the capacitor is charged with a current I, the voltage
across the capacitor rises linearly with time. When this voltage
reaches the level of comparator #1 (set at 2/3 of the supply
voltage), the flip-flop is triggered, changes states, and
releases current source #2. This current source normally
carries a current 2I, thus the capacitor is discharged with a

net-current I and the voltage across it drops linearly with time.
When it has reached the level of comparator #2 (set at 1/3 of
the supply voltage), the flip-flop is triggered into its original
state and the cycle starts again.

Four waveforms are readily obtainable from this basic
generator circuit. With the current sources set at I and 2I
respectively, the charge and discharge times are equal.
Thus a triangle waveform is created across the capacitor
and the flip-flop produces a square wave. Both waveforms
are fed to buffer stages and are available at pins 3 and 9.

Detailed Schematic

ICL8038

6 9

N.C.

C
3300pF

82K

10K

TRI

SINE

-10V

+10V

FIGURE 1. TEST CIRCUIT

11K

39K

EXT

COMPARATOR

27K

BUFFER AMPLIFIER

27K

4.7K

27K

620

1.8K

100

30K

40K

EXT

10K

15K

270

2.7K

470

800

10K

2.7K

800

FLIP-FLOP

SINE CONVERTER

V+

5.2K

200

375

330

1600

330

375

200

5.6K

EXT

82K

2.7K

10K

33K

CURRENT SOURCES

ICL8038

The levels of the current sources can, however, be selected
over a wide range with two external resistors. Therefore, with
the two currents set at values different from I and 2I, an
asymmetrical sawtooth appears at Terminal 3 and pulses
with a duty cycle from less than 1% to greater than 99% are
available at Terminal 9.

The sine wave is created by feeding the triangle wave into a
nonlinear network (sine converter). This network provides a
decreasing shunt impedance as the potential of the triangle
moves toward the two extremes.

Waveform Timing

The symmetry of all waveforms can be adjusted with the
external timing resistors. Two possible ways to accomplish
this are shown in Figure 3. Best results are obtained by
keeping the timing resistors R

and R

separate (A). R

controls the rising portion of the triangle and sine wave and
the 1 state of the square wave.

The magnitude of the triangle waveform is set at

SUPPLY

; therefore the rising portion of the triangle is,

The falling portion of the triangle and sine wave and the 0
state of the square wave is:

Thus a 50% duty cycle is achieved when R

= R

If the duty cycle is to be varied over a small range about 50%
only, the connection shown in Figure 3B is slightly more
convenient. A 1k

Ω potentiometer may not allow the duty cycle

to be adjusted through 50% on all devices. If a 50% duty cycle
is required, a 2k

Ω or 5kΩ potentiometer should be used.

With two separate timing resistors, the frequency is given by:

or, if R

= R

C V

--------------

C 1/3 V

SUPPLY

0.22 V

SUPPLY

-------------------------------------------------------------------

0.66

------------------

-------------

1/3V

SUPPLY

2 0.22

(

)

SUPPLY

------------------------

0.22

SU PPLY

------------------------

-----------------------------------------------------------------------------------

0.66 2RA RB

(

)

-------------------------------------

----------------

0.66

------------

-------------------------

•Ž

•Žœ

•ŽŸ

•Ž›

•Žž

------------------------------------------------------

0.33

-----------

(for Figure 3A)

FIGURE 2A. SQUARE WAVE DUTY CYCLE - 50%

FIGURE 2B. SQUARE WAVE DUTY CYCLE - 80%

FIGURE 2. PHASE RELATIONSHIP OF WAVEFORMS

FIGURE 3A.

FIGURE 3B.

FIGURE 3. POSSIBLE CONNECTIONS FOR THE EXTERNAL TIMING RESISTORS

82K

ICL8038

6 9

V- OR GND

V+

ICL8038

6 9

100K

V- OR GND

V+

Ω

ICL8038

Neither time nor frequency are dependent on supply voltage,
even though none of the voltages are regulated inside the
integrated circuit. This is due to the fact that both currents
and thresholds are direct, linear functions of the supply
voltage and thus their effects cancel.

Reducing Distortion

To minimize sine wave distortion the 82k

Ω resistor between

pins 11 and 12 is best made variable. With this arrangement
distortion of less than 1% is achievable. To reduce this even
further, two potentiometers can be connected as shown in
Figure 4; this configuration allows a typical reduction of sine
wave distortion close to 0.5%.

Selecting R

, R

and C

For any given output frequency, there is a wide range of RC
combinations that will work, however certain constraints are
placed upon the magnitude of the charging current for
optimum performance. At the low end, currents of less than
1

μA are undesirable because circuit leakages will contribute

significant errors at high temperatures. At higher currents
(I > 5mA), transistor betas and saturation voltages will
contribute increasingly larger errors. Optimum performance
will, therefore, be obtained with charging currents of 10

μA to

1mA. If pins 7 and 8 are shorted together, the magnitude of
the charging current due to R

can be calculated from:

and R

are shown in the Detailed Schematic.

A similar calculation holds for R

The capacitor value should be chosen at the upper end of its
possible range.

Waveform Out Level Control and Power Supplies

The waveform generator can be operated either from a
single power supply (10V to 30V) or a dual power supply
(

±5V to ±15V). With a single power supply the average

levels of the triangle and sine wave are at exactly one-half of
the supply voltage, while the square wave alternates
between V+ and ground. A split power supply has the
advantage that all waveforms move symmetrically about
ground.

The square wave output is not committed. A load resistor
can be connected to a different power supply, as long as the
applied voltage remains within the breakdown capability of
the waveform generator (30V). In this way, the square wave
output can be made TTL compatible (load resistor
connected to +5V) while the waveform generator itself is
powered from a much higher voltage.

Frequency Modulation and Sweeping

The frequency of the waveform generator is a direct function
of the DC voltage at Terminal 8 (measured from V+). By
altering this voltage, frequency modulation is performed. For
small deviations (e.g.

±10%) the modulating signal can be

applied directly to pin 8, merely providing DC decoupling
with a capacitor as shown in Figure 5A. An external resistor
between pins 7 and 8 is not necessary, but it can be used to
increase input impedance from about 8k

Ω (pins 7 and 8

connected together), to about (R + 8k

Ω).

For larger FM deviations or for frequency sweeping, the
modulating signal is applied between the positive supply
voltage and pin 8 (Figure 5B). In this way the entire bias for
the current sources is created by the modulating signal, and
a very large (e.g. 1000:1) sweep range is created
(f = Minimum at V

SWEEP

= 0, i.e., Pin 8 = V+). Care must be

taken, however, to regulate the supply voltage; in this
configuration the charge current is no longer a function of the
supply voltage (yet the trigger thresholds still are) and thus
the frequency becomes dependent on the supply voltage.
The potential on Pin 8 may be swept down from V+ by (

SUPPLY

- 2V).

ICL8038

6 9

100k

Ω

V- OR GND

V+

Ω

10k

Ω

100k

Ω

10k

Ω

FIGURE 4. CONNECTION TO ACHIEVE MINIMUM SINE

WAVE DISTORTION

V+

V-

(

)

(

)

----------------------------------------

--------

0.22 V+ V-

(

)

------------------------------------

81K

ICL8038

6 9

V- OR GND

V+

FIGURE 5A. CONNECTIONS FOR FREQUENCY MODULATION

ICL8038

Typical Applications

The sine wave output has a relatively high output impedance
(1k

Ω Typ). The circuit of Figure 6 provides buffering, gain

and amplitude adjustment. A simple op amp follower could
also be used.

With a dual supply voltage the external capacitor on Pin 10 can
be shorted to ground to halt the ICL8038 oscillation. Figure 7
shows a FET switch, diode ANDed with an input strobe signal
to allow the output to always start on the same slope.

To obtain a 1000:1 Sweep Range on the ICL8038 the
voltage across external resistors R

and R

must decrease

to nearly zero. This requires that the highest voltage on
control Pin 8 exceed the voltage at the top of R

and R

a few hundred mV. The Circuit of Figure 8 achieves this by
using a diode to lower the effective supply voltage on the
ICL8038. The large resistor on pin 5 helps reduce duty cycle
variations with sweep.

The linearity of input sweep voltage versus output frequency
can be significantly improved by using an op amp as shown
in Figure 10.

81K

ICL8038

6 9

V- OR GND

V+

SWEEP

VOLTAGE

FIGURE 5B. CONNECTIONS FOR FREQUENCY SWEEP

FIGURE 5.

ICL8038

6 2

100K

V-

V+

AMPLITUDE

20K

741

4.7K

FIGURE 6. SINE WAVE OUTPUT BUFFER AMPLIFIERS

ICL8038

1N914

-15V

V+

STROBE

2N4392

1N914

15K

100K

OFF

+15V (+10V)
-15V (-10V)

FIGURE 7. STROBE TONE BURST GENERATOR

0.0047

μF

DISTORTION

ICL8038

6 9

4.7K

-10V

+10V

20K

4.7K

DUTY CYCLE

15K

1N457

0.1

μF

100K

•‰ˆ

15M

10K

FREQ.

FIGURE 8. VARIABLE AUDIO OSCILLATOR, 20Hz TO 20kHzY

ICL8038

Use in Phase Locked Loops

Its high frequency stability makes the ICL8038 an ideal
building block for a phase locked loop as shown in Figure 9.
In this application the remaining functional blocks, the phase
detector and the amplifier, can be formed by a number of
available ICs (e.g., MC4344, NE562).

In order to match these building blocks to each other, two
steps must be taken. First, two different supply voltages are
used and the square wave output is returned to the supply of
the phase detector. This assures that the VCO input voltage
will not exceed the capabilities of the phase detector. If a
smaller VCO signal is required, a simple resistive voltage
divider is connected between pin 9 of the waveform
generator and the VCO input of the phase detector.

Second, the DC output level of the amplifier must be made
compatible to the DC level required at the FM input of the
waveform generator (pin 8, 0.8V+). The simplest solution here
is to provide a voltage divider to V+ (R

, R

as shown) if the

amplifier has a lower output level, or to ground if its level is
higher. The divider can be made part of the low-pass filter.

This application not only provides for a free-running
frequency with very low temperature drift, but is also has the
unique feature of producing a large reconstituted sinewave
signal with a frequency identical to that at the input.

For further information, see Intersil Application Note AN013,
†œEverything You Always Wanted to Know About the ICL8038†.

SINE WAVE

ICL8038

6 3

V-/GND

DUTY

CYCLE

FREQUENCY

ADJUST

ADJ.

SINE WAVE

TRIANGLE

OUT

SINE WAVE
ADJ.

TIMING
CAP.

FM BIAS

SQUARE

WAVE

OUT

LOW PASS

FILTER

DEMODULATED

AMPLIFIER

PHASE

DETECTOR

VCO

INPUT

OUT

FIGURE 9. WAVEFORM GENERATOR USED AS STABLE VCO IN A PHASE-LOCKED LOOP

3,900pF

SINE WAVE

ICL8038

4.7k

Ω

4.7k

Ω

500

Ω

10k

Ω

1N753A

DISTORTION

FUNCTION GENERATOR

100k

Ω

μF

15V

Ω

(6.2V)

HIGH FREQUENCY

SYMMETRY

100k

Ω

LOW FREQUENCY
SYMMETRY

100k

Ω

741

+15V

-15V

SINE WAVE
OUTPUT

741

+15V

Ω

10k

Ω

OFFSET

-V

1,000pF

Ω

FIGURE 10. LINEAR VOLTAGE CONTROLLED OSCILLATOR

ICL8038

Definition of Terms

Supply Voltage (V

SUPPLY

). The total supply voltage from

V+ to V-.

Supply Current. The supply current required from the
power supply to operate the device, excluding load currents
and the currents through R

and R

Frequency Range. The frequency range at the square wave
output through which circuit operation is guaranteed.

Sweep FM Range. The ratio of maximum frequency to
minimum frequency which can be obtained by applying a
sweep voltage to pin 8. For correct operation, the sweep
voltage should be within the range:

(

SUPPLY

+ 2V) < V

SWEEP

< V

SUPPLY

FM Linearity. The percentage deviation from the best fit
straight line on the control voltage versus output frequency
curve.

Output Amplitude. The peak-to-peak signal amplitude
appearing at the outputs.

Saturation Voltage. The output voltage at the collector of
Q

when this transistor is turned on. It is measured for a

sink current of 2mA.

Rise and Fall Times. The time required for the square wave
output to change from 10% to 90%, or 90% to 10%, of its
final value.

Triangle Waveform Linearity. The percentage deviation
from the best fit straight line on the rising and falling triangle
waveform.

Total Harmonic Distortion. The total harmonic distortion at
the sine wave output.

Typical Performance Curves

FIGURE 11. SUPPLY CURRENT vs SUPPLY VOLTAGE

FIGURE 12. FREQUENCY vs SUPPLY VOLTAGE

FIGURE 13. FREQUENCY vs TEMPERATURE

FIGURE 14. SQUARE WAVE OUTPUT RISE/FALL TIME vs

LOAD RESISTANCE

SUPPLY VOLTAGE (V)

SUPPLY

CURRENT (

125

-55

SUPPLY VOLTAGE (V)

NORMALIZE

FREQU

NCY

0.98

0.99

1.01

1.03

1.00

1.02

TEMPERATURE (

NORMA

IZED F

UENCY

-50

-25

125

0.98

0.99

1.01

1.03

1.00

1.02

30V

20V
10V

20V

30V

10V

LOAD RESISTANCE (k

Ω)

100

150

200

TIME

(ns

)

125

FALL TIME

RISE TIME

-55

125

-55

ICL8038

FIGURE 15. SQUARE WAVE SATURATION VOLTAGE vs

LOAD CURRENT

FIGURE 16. TRIANGLE WAVE OUTPUT VOLTAGE vs LOAD

CURRENT

FIGURE 17. TRIANGLE WAVE OUTPUT VOLTAGE vs

FREQUENCY

FIGURE 18. TRIANGLE WAVE LINEARITY vs FREQUENCY

FIGURE 19. SINE WAVE OUTPUT VOLTAGE vs FREQUENCY

FIGURE 20. SINE WAVE DISTORTION vs FREQUENCY

Typical Performance Curves

(Continued)

LOAD CURRENT (mA)

TURATION V

LTAGE

1.5

1.0

0.5

125

-55

LOAD CURRENT (mA)

NORMA

IZED PEAK OUTPUT

LTAGE

0.8

0.9

1.0

LOAD CURRENT

LOAD CURRENT TO V+

125

-55

TO V -

FREQUENCY (Hz)

10K

100

100K

0.6

0.7

0.8

0.9

1.0

1.1

1.2

NORMALIZED OUTPUT VOLTAGE

FREQUENCY (Hz)

10K

100

100K

0.01

0.1

1.0

10.0

LINEARITY

(%)

FREQUENCY (Hz)

10K

100

100K

0.9

1.0

1.1

NORMALIZ

OUT

VOLT

AGE

ADJUSTED

FREQUENCY (Hz)

10K

100

100K

DIS

ORT

)

UNADJUSTED

ICL8038

Dual-In-Line Plastic Packages (PDIP)

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between English

and Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the †œMO Series Symbol List† in Section 2.2 of

Publication No. 95.

4. Dimensions A, A1 and L are measured with the package seated in

JEDEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protrusions.

Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).

6. E and

are measured with the leads constrained to be perpen-

dicular to datum

7. e

and e

are measured at the lead tips with the leads uncon-

strained. e

must be zero or greater.

8. B1 maximum dimensions do not include dambar protrusions. Dambar

protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,

E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 -
1.14mm).

-C-

-B-

INDEX

1 2 3

N/2

AREA

SEATING

BASE

PLANE

-C-

-A-

0.010 (0.25)

C A

B S

E14.3

(JEDEC MS-001-AA ISSUE D)

14 LEAD DUAL-IN-LINE PLASTIC PACKAGE

SYMBOL

INCHES

MILLIMETERS

NOTES

MIN

MAX

MIN

MAX

0.210

5.33

0.015

0.39

0.115

0.195

2.93

4.95

0.014

0.022

0.356

0.558

0.045

0.070

1.15

1.77

0.008

0.014

0.204

0.355

0.735

0.775

18.66

19.68

0.005

0.13

0.300

0.325

7.62

8.25

0.240

0.280

6.10

7.11

0.100 BSC

2.54 BSC

0.300 BSC

7.62 BSC

0.430

10.92

0.115

0.150

2.93

3.81

Rev. 0 12/93

All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. How-
ever, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site www.intersil.com

Sales Office Headquarters

NORTH AMERICA
Intersil Corporation
2401 Palm Bay Rd., Mail Stop 53-204
Palm Bay, FL 32905
TEL: (321) 724-7000
FAX: (321) 724-7240

EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05

ASIA
Intersil Ltd.
8F-2, 96, Sec. 1, Chien-kuo North,
Taipei, Taiwan 104
Republic of China
TEL: 886-2-2515-8508
FAX: 886-2-2515-8369

ICL8038

Ceramic Dual-In-Line Frit Seal Packages (CERDIP)

NOTES:

1. Index area: A notch or a pin one identification mark shall be locat-

ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.

2. The maximum limits of lead dimensions b and c or M shall be

measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.

3. Dimensions b1 and c1 apply to lead base metal only. Dimension

M applies to lead plating and finish thickness.

4. Corner leads (1, N, N/2, and N/2+1) may be configured with a

partial lead paddle. For this configuration dimension b3 replaces
dimension b2.

5. This dimension allows for off-center lid, meniscus, and glass

overrun.

6. Dimension Q shall be measured from the seating plane to the

base plane.

7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.

10. Controlling dimension: INCH.

bbb

C A - B

SEATING

BASE

PLANE

-D-

-A-

-C-

-B-

(c)

(b)

SECTION A-A

BASE

LEAD FINISH

METAL

A/2

ccc

C A - B

aaa

C A - B

F14.3

MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A)

14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE

SYMBOL

INCHES

MILLIMETERS

NOTES

MIN

MAX

MIN

MAX

0.200

5.08

0.014

0.026

0.36

0.66

0.014

0.023

0.36

0.58

0.045

0.065

1.14

1.65

0.023

0.045

0.58

1.14

0.008

0.018

0.20

0.46

0.008

0.015

0.20

0.38

0.785

19.94

0.220

0.310

5.59

7.87

0.100 BSC

2.54 BSC

0.300 BSC

7.62 BSC

eA/2

0.150 BSC

3.81 BSC

0.125

0.200

3.18

5.08

0.015

0.060

0.38

1.52

0.005

0.13

105

aaa

0.015

0.38

bbb

0.030

0.76

ccc

0.010

0.25

0.0015

0.038

2, 3

Rev. 0 4/94