IRF840, SiHF840
www.vishay.com
Vishay Siliconix
S16-0754-Rev. D, 02-May-16
1
Document Number: 91070
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
Power MOSFET
FEATURES
Dynamic dV/dt rating
Repetitive avalanche rated
Fast switching
Ease of paralleling
Simple drive requirements
Material categorization: for definitions of compliance
please see
www.vishay.com/doc?99912
Note
*
This datasheet provides information about parts that are
RoHS-compliant and / or parts that are non-RoHS-compliant. For
example, parts with lead (Pb) terminations are not RoHS-compliant.
Please see the information / tables in this datasheet for details.
DESCRIPTION
Third generation power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness.
The TO-220AB package is universally preferred for all commercial-industrial applications at power dissipation levels to approximately 50 W. The low thermal resistance and low package cost of the TO-220AB contribute to its wide acceptance throughout the industry.
Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. V
DD
= 50 V, starting T
J
= 25 C, L = 14 mH, R
g
= 25
Ω, I
AS
= 8.0 A (see fig. 12).
c. I
SD
8.0 A, dI/dt 100 A/μs, V
DD
V
DS
, T
J
150 C.
d. 1.6 mm from case.
PRODUCT SUMMARY
V
DS
(V)
500
R
DS(on)
(
Ω)
V
GS
= 10 V
0.85
Q
g
max. (nC)
63
Q
gs
(nC)
9.3
Q
gd
(nC)
32
Configuration
Single
N-Channel MOSFET
G
D
S
TO-220AB
G
D
S
Available
Available
ORDERING INFORMATION
Package
TO-220AB
Lead (Pb)-free
IRF840PbF
SiHF840-E3
SnPb
IRF840
SiHF840
ABSOLUTE MAXIMUM RATINGS (T
C
= 25 C, unless otherwise noted)
PARAMETER SYMBOL
LIMIT
UNIT
Drain-Source Voltage
V
DS
500
V
Gate-Source Voltage
V
GS
20 V
Continuous Drain Current
V
GS
at 10 V
T
C
= 25 C
I
D
8.0
A
T
C
= 100 C
5.1
Pulsed Drain Current
a
I
DM
32
Linear Derating Factor
1.0
W/ C
Single Pulse Avalanche Energy
b
E
AS
510
mJ
Repetitive Avalanche Current
a
I
AR
8.0
A
Repetitive Avalanche Energy
a
E
AR
13
mJ
Maximum Power Dissipation
T
C
= 25 C
P
D
125
W
Peak Diode Recovery dV/dt
c
dV/dt 3.5
V/ns
Operating Junction and Storage Temperature Range
T
J
, T
stg
-55 to +150
C
Soldering Recommendations (Peak temperature)
d
for 10 s
300
Mounting Torque
6-32 or M3 screw
10 lbf
in
1.1
N m
IRF840, SiHF840
www.vishay.com
Vishay Siliconix
S16-0754-Rev. D, 02-May-16
2
Document Number: 91070
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width
300 μs; duty cycle 2 %.
THERMAL RESISTANCE RATINGS
PARAMETER SYMBOL
TYP.
MAX.
UNIT
Maximum Junction-to-Ambient
R
thJA
-
62
C/W
Case-to-Sink, Flat, Greased Surface
R
thCS
0.50
-
Maximum Junction-to-Case (Drain)
R
thJC
-
1.0
SPECIFICATIONS (T
J
= 25 C, unless otherwise noted)
PARAMETER SYMBOL
TEST
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
V
DS
V
GS
= 0 V, I
D
= 250 μA
500
-
-
V
V
DS
Temperature Coefficient
V
DS
/T
J
Reference to 25 C, I
D
= 1 mA
-
0.78
-
V/ C
Gate-Source Threshold Voltage
V
GS(th)
V
DS
= V
GS
, I
D
= 250 μA
2.0
-
4.0
V
Gate-Source Leakage
I
GSS
V
GS
= 20 V
-
-
100
nA
Zero Gate Voltage Drain Current
I
DSS
V
DS
= 500 V, V
GS
= 0 V
-
-
25
μA
V
DS
= 400 V, V
GS
= 0 V, T
J
= 125 C
-
-
250
Drain-Source On-State Resistance
R
DS(on)
V
GS
= 10 V
I
D
= 4.8 A
b
-
-
0.85
Ω
Forward Transconductance
g
fs
V
DS
= 50 V, I
D
= 4.8 A
b
4.9
-
-
S
Dynamic
Input Capacitance
C
iss
V
GS
= 0 V,
V
DS
= 25 V,
f = 1.0 MHz, see fig. 5
-
1300
-
pF
Output Capacitance
C
oss
-
310
-
Reverse Transfer Capacitance
C
rss
-
120
-
Total Gate Charge
Q
g
V
GS
= 10 V
I
D
= 8 A, V
DS
= 400 V,
see fig. 6 and 13
b
-
-
63
nC
Gate-Source Charge
Q
gs
-
-
9.3
Gate-Drain Charge
Q
gd
-
-
32
Turn-On Delay Time
t
d(on)
V
DD
= 250 V, I
D
= 8 A
R
g
= 9.1
Ω, R
D
= 31
Ω, see fig. 10
b
-
14
-
ns
Rise Time
t
r
-
23
-
Turn-Off Delay Time
t
d(off)
-
49
-
Fall Time
t
f
-
20
-
Internal Drain Inductance
L
D
Between lead,
6 mm (0.25") from package and center of die contact
-
4.5
-
nH
Internal Source Inductance
L
S
-
7.5
-
Gate Input Resistance
R
g
f = 1 MHz, open drain
0.6
-
2.8
Ω
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
I
S
MOSFET symbol showing the
integral reverse
p - n junction diode
-
-
8.0
A
Pulsed Diode Forward Current
a
I
SM
-
-
32
Body Diode Voltage
V
SD
T
J
= 25 C, I
S
= 8 A, V
GS
= 0 V
b
-
-
2.0
V
Body Diode Reverse Recovery Time
t
rr
T
J
= 25 C, I
F
= 8 A, dI/dt = 100 A/μs
b
-
460
970
ns
Body Diode Reverse Recovery Charge
Q
rr
-
4.2
8.9
μC
Forward Turn-On Time
t
on
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
and L
D
)
D
S
G
S
D
G
IRF840, SiHF840
www.vishay.com
Vishay Siliconix
S16-0754-Rev. D, 02-May-16
3
Document Number: 91070
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (25 C, unless otherwise noted)
Fig. 1 - Typical Output Characteristics, T
C
= 25 C
Fig. 2 - Typical Output Characteristics, T
C
= 150 C
Fig. 3 - Typical Transfer Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Typical Gate Charge vs. Drain-to-Source Voltage
91070_01
V
DS
, Drain-to-Source Voltage (V)
I
D
, Dr
ain Current (A)
10
1
10
0
10
0
10
1
Bottom
Top
V
GS
15 V
10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V 4.5 V
20 s Pulse Width T
C
=
25 C
4.5 V
91070_02
10
1
10
0
10
0
10
1
I
D
, Dr
ain Current (A)
4.5 V
Bottom
Top
V
GS
15 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V 4.5 V
20 s Pulse Width T
C
=
150 C
V
DS,
Drain-to-Source Voltage (V)
91070_03
25
C
150
C
20 s Pulse Width V
DS
=
50 V
10
1
10
0
I
D
, Dr
ain Current (A)
V
GS,
Gate-to-Source Voltage (V)
5
6
7
8
9
10
4
91070_04
3.0
0.0
0.5
1.0
1.5
2.0
2.5
- 60 - 40 - 20
0
20
40
60 80 100 120 140 160
T
J,
Junction Temperature ( C)
R
DS(on)
, Dr
ain-to-Source On Resistance
(Nor
maliz
ed)
I
D
= 8.0 A
V
GS
= 10 V
91070_05
2500
2000
1500
1000
0
500
10
0
10
1
Capacitance (pF)
V
DS,
Drain-to-Source Voltage (V)
C
iss
C
rss
C
oss
V
GS
= 0 V, f = 1 MHz
C
iss
= C
gs
+ C
gd
, C
ds
Shorted
C
rss
= C
gd
C
oss
= C
ds
+ C
gd
91070_06
Q
G
, Total Gate Charge (nC)
V
GS
, Gate-to-Source
V
o
ltage (V)
20
16
12
8
0
4
0
15
75
60
45
30
I
D
= 8.0 A
For test circuit see figure 13
V
DS
= 250 V
V
DS
= 100 V
V
DS
= 400 V
IRF840, SiHF840
www.vishay.com
Vishay Siliconix
S16-0754-Rev. D, 02-May-16
4
Document Number: 91070
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 10a - Switching Time Test Circuit
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
91070_07
10
1
10
0
V
SD
, Source-to-Drain Voltage (V)
I
SD
, Re
v
e
rse Dr
ain Current (A)
0.4
1.0
0.8
0.6
25
C
150
C
V
GS
= 0 V
1.4
1.2
91070_08
10
s
100
s
1
ms
10
ms
T
C
= 25 C
T
J
= 150 C
Single Pulse
V
DS
, Drain-to-Source Voltage (V)
I
D
, Dr
ain Current (A)
10
2
0.1
2
5
2
1
5
10
2
5
2
5
1
2
5
10
2
5
10
2
2
5
10
3
2
5
10
4
0.1
Operation in this area limited
by R
DS(on)
91070_09
I
D
, Dr
ain Current (A)
T
C
, Case Temperature ( C)
0.0
2.0
4.0
6.0
8.0
25
150
125
100
75
50
Pulse width
≤ 1 s
Duty factor
≤ 0.1 %
R
D
V
GS
R
G
D.U.T.
10 V
+
-
V
DS
V
DD
V
DS
90 %
10 %
V
GS
t
d(on)
t
r
t
d(off)
t
f
0
- 0.5
0.2
0.1 0.05
0.02 0.01
Single Pulse (Thermal Response)
P
DM
t
1
t
2
Notes: 1. Duty Factor, D = t
1
/t
2
2. Peak T
j
= P
DM
x Z
thJC
+ T
C
Ther
mal Response (Z
th
JC
)
10
-5
10
-4
10
-3
10
-2
0.1
1
10
10
2
10
1
0.1
10
-3
10
-2
IRF840, SiHF840
www.vishay.com
Vishay Siliconix
S16-0754-Rev. D, 02-May-16
5
Document Number: 91070
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
Fig. 12a - Unclamped Inductive Test Circuit
Fig. 12b - Unclamped Inductive Waveforms
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Fig. 13a - Basic Gate Charge Waveform
Fig. 13b - Gate Charge Test Circuit
R
G
I
AS
0.01
Ω
t
p
D.U.T.
L
V
DS
+
-
V
DD
10 V
Vary t
p
to obtain
required I
AS
I
AS
V
DS
V
DD
V
DS
t
p
91070_12c
Bottom
Top
I
D
3.6 A 5.1 A 8.0 A
V
DD
= 50 V
1200
0
200
400
600
800
1000
25
150
125
100
75
50
Starting T
J
, Junction Temperature ( C)
E
AS
, Single Pulse Energy (mJ)
Q
GS
Q
GD
Q
G
V
G
Charge
10 V
D.U.T.
3 mA
V
GS
V
DS
I
G
I
D
0.3 F
0.2 F
50 k
Ω
12 V
Current regulator
Current sampling resistors
Same type as D.U.T.
+
-
IRF840, SiHF840
www.vishay.com
Vishay Siliconix
S16-0754-Rev. D, 02-May-16
6
Document Number: 91070
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see
www.vishay.com/ppg?91070
.
P.W.
Period
dI/dt
Diode recovery
dV/dt
Ripple ≤ 5 %
Body diode forward drop
Re-applied voltage
Reverse recovery current
Body diode forward
current
V
GS
= 10 V
a
V
DD
I
SD
Driver gate drive
D.U.T. I
SD
waveform
D.U.T. V
DS
waveform
Inductor current
D =
P.W.
Period
+
-
+
+
+
-
-
-
Note a. V
GS
= 5 V for logic level devices
Peak Diode Recovery dV/dt Test Circuit
V
DD
dV/dt controlled by R
g
Driver same type as D.U.T. I
SD
controlled by duty factor D
D.U.T. - device under test
D.U.T.
Circuit layout considerations Low stray inductance
Ground plane Low leakage inductance
current transformer
R
g
Package Information
www.vishay.com
Vishay Siliconix
Revison: 14-Dec-15
1
Document Number: 66542
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
TO-220-1
Note
M* = 0.052 inches to 0.064 inches (dimension including
protrusion), heatsink hole for HVM
M
*
3
2
1
L
L(1)
D
H(1)
Q
Ø P
A
F
J(1)
b(1)
e(1)
e
E
b
C
DIM.
MILLIMETERS
INCHES
MIN.
MAX.
MIN.
MAX.
A
4.24
4.65
0.167
0.183
b
0.69
1.02
0.027
0.040
b(1)
1.14
1.78
0.045
0.070
c
0.36
0.61
0.014
0.024
D
14.33
15.85
0.564
0.624
E
9.96
10.52
0.392
0.414
e
2.41
2.67
0.095
0.105
e(1)
4.88
5.28
0.192
0.208
F
1.14
1.40
0.045
0.055
H(1)
6.10
6.71
0.240
0.264
J(1)
2.41
2.92
0.095
0.115
L
13.36
14.40
0.526
0.567
L(1)
3.33
4.04
0.131
0.159
Ø P
3.53
3.94
0.139
0.155
Q
2.54
3.00
0.100
0.118
ECN: X15-0364-Rev. C, 14-Dec-15 DWG: 6031
Package Picture
ASE
Xian
Legal Disclaimer Notice
www.vishay.com
Vishay
Revision: 13-Jun-16
1
Document Number: 91000
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
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