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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SNOSC16D - MARCH 2000 - REVISED JANUARY 2015
LMx24-N, LM2902-N Low-Power, Quad-Operational Amplifiers
1
1 Features
1
•
Internally Frequency Compensated for Unity Gain
•
Large DC Voltage Gain 100 dB
•
Wide Bandwidth (Unity Gain) 1 MHz
(Temperature Compensated)
•
Wide Power Supply Range:
-
Single Supply 3 V to 32 V
-
or Dual Supplies ±1.5 V to ±16 V
•
Very Low Supply Current Drain (700
μA)
—Essentially Independent of Supply Voltage
•
Low Input Biasing Current 45 nA
(Temperature Compensated)
•
Low Input Offset Voltage 2 mV
and Offset Current: 5 nA
•
Input Common-Mode Voltage Range Includes
Ground
•
Differential Input Voltage Range Equal to the
Power Supply Voltage
•
Large Output Voltage Swing 0 V to V
+
- 1.5 V
•
Advantages:
-
Eliminates Need for Dual Supplies
-
Four Internally Compensated Op Amps in a
Single Package
-
Allows Direct Sensing Near GND and V
OUT
also Goes to GND
-
Compatible With All Forms of Logic
-
Power Drain Suitable for Battery Operation
-
In the Linear Mode the Input Common-Mode,
Voltage Range Includes Ground and the
Output Voltage
-
Can Swing to Ground, Even Though Operated
from Only a Single Power Supply Voltage
-
Unity Gain Cross Frequency is Temperature
Compensated
-
Input Bias Current is Also Temperature
Compensated
2 Applications
•
Transducer Amplifiers
•
DC Gain Blocks
•
Conventional Op Amp Circuits
3 Description
The LM124-N series consists of four independent,
high-gain,
internally
frequency
compensated
operational amplifiers designed to operate from a
single power supply over a wide range of voltages.
Operation from split-power supplies is also possible
and
the
low-power
supply
current
drain
is
independent of the magnitude of the power supply
voltage.
Application areas include transducer amplifiers, DC
gain blocks and all the conventional op amp circuits
which now can be more easily implemented in single
power supply systems. For example, the LM124-N
series can directly operate off of the standard 5-V
power supply voltage which is used in digital systems
and easily provides the required interface electronics
without requiring the additional ±15 V power supplies.
Device
PART NUMBER
PACKAGE
BODY SIZE (NOM)
LM124-N
CDIP (14)
19.56 mm × 6.67 mm
LM224-N
LM324-N
CDIP (14)
19.56 mm × 6.67 mm
PDIP (14)
19.177 mm × 6.35 mm
SOIC (14)
8.65 mm × 3.91 mm
TSSOP (14)
5.00 mm × 4.40 mm
LM2902-N
PDIP (14)
19.177 mm × 6.35 mm
SOIC (14)
8.65 mm × 3.91 mm
TSSOP (14)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Schematic Diagram
2
,
SNOSC16D - MARCH 2000 - REVISED JANUARY 2015
Product Folder Links:
Copyright © 2000-2015, Texas Instruments Incorporated
Table of Contents
1
Features ..................................................................
2
Applications ...........................................................
3
Description .............................................................
4
Revision History.....................................................
5
Pin Configuration and Functions .........................
6
Specifications.........................................................
6.1
Absolute Maximum Ratings ......................................
6.2
ESD Ratings..............................................................
6.3
Recommended Operating Conditions .......................
6.4
Thermal Information ..................................................
6.5
Electrical Characteristics: LM124A/224A/324A ........
6.6
Electrical Characteristics: LM124-N/224-N/324-
N/2902-N ...................................................................
6.7
Typical Characteristics ..............................................
7
Detailed Description ............................................
7.1
Overview .................................................................
7.2
Functional Block Diagram .......................................
7.3
Feature Description.................................................
7.4
Device Functional Modes........................................
8
Application and Implementation ........................
8.1
Application Information............................................
8.2
Typical Applications ...............................................
9
Power Supply Recommendations ......................
10
Layout...................................................................
10.1
Layout Guidelines .................................................
10.2
Layout Example ....................................................
11
Device and Documentation Support .................
11.1
Related Links ........................................................
11.2
Trademarks ...........................................................
11.3
Electrostatic Discharge Caution ............................
11.4
Glossary ................................................................
12
Mechanical, Packaging, and Orderable
Information ...........................................................
4 Revision History
Changes from Revision C (November 2012) to Revision D
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ...............................
3
SNOSC16D - MARCH 2000 - REVISED JANUARY 2015
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5 Pin Configuration and Functions
J Package
14-Pin CDIP
Top View
D Package
14-Pin SOIC
Top View
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
OUTPUT1
1
O
Output, Channel 1
INPUT1-
2
I
Inverting Input, Channel 1
INPUT1+
3
I
Noninverting Input, Channel 1
V+
4
P
Positive Supply Voltage
INPUT2+
5
I
Nonnverting Input, Channel 2
INPUT2-
6
I
Inverting Input, Channel 2
OUTPUT2
7
O
Output, Channel 2
OUTPUT3
8
O
Output, Channel 3
INPUT3-
9
I
Inverting Input, Channel 3
INPUT3+
10
I
Noninverting Input, Channel 3
GND
11
P
Ground or Negative Supply Voltage
INPUT4+
12
I
Noninverting Input, Channel 4
INPUT4-
13
I
Inverting Input, Channel 4
OUTPUT4
14
O
Output, Channel 4
4
,
SNOSC16D - MARCH 2000 - REVISED JANUARY 2015
Product Folder Links:
Copyright © 2000-2015, Texas Instruments Incorporated
(1)
Refer to RETS124AX for LM124A military specifications and refer to RETS124X for LM124-N military specifications.
(2)
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3)
This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of
the input PNP transistors becoming forward biased and thereby acting as input diode clamps. In addition to this diode action, there is
also lateral NPN parasitic transistor action on the IC chip. This transistor action can cause the output voltages of the op amps to go to
the V
+
voltage level (or to ground for a large overdrive) for the time duration that an input is driven negative. This is not destructive and
normal output states will re-establish when the input voltage, which was negative, again returns to a value greater than
-0.3 V (at 25 °C).
(4)
For operating at high temperatures, the LM324-N/LM324A/LM2902-N must be derated based on a 125 °C maximum junction
temperature and a thermal resistance of 88 °C/W which applies for the device soldered in a printed circuit board, operating in a still air
ambient. The LM224-N/LM224A and LM124-N/LM124A can be derated based on a 150 °C maximum junction temperature. The
dissipation is the total of all four amplifiers—use external resistors, where possible, to allow the amplifier to saturate of to reduce the
power which is dissipated in the integrated circuit.
(5)
Short circuits from the output to V
+
can cause excessive heating and eventual destruction. When considering short circuits to ground,
the maximum output current is approximately 40 mA independent of the magnitude of V
+
. At values of supply voltage in excess of 15 V,
continuous short-circuits can exceed the power dissipation ratings and cause eventual destruction. Destructive dissipation can result
from simultaneous shorts on all amplifiers.
6 Specifications
6.1 Absolute Maximum Ratings
See
(1) (2)
.
LM124-N/LM224-N/LM324-N
LM124A/LM224A/LM324A
LM2902-N
MIN
MAX
MIN
MAX
UNIT
Supply Voltage, V
+
32
26
V
Differential Input Voltage
32
26
V
Input Voltage
-0.3
32
-0.3
26
V
Input Current (V
IN
<
-0.3 V)
(3)
50
50
mA
Power
Dissipation
(4)
PDIP
1130
1130
mW
CDIP
1260
1260
mW
SOIC Package
800
800
mW
Output Short-Circuit to GND
(One Amplifier)
(5)
V
+
≤ 15 V and T
A
= 25 °C
Continuous
Continuous
Lead Temperature (Soldering, 10 seconds)
260
260
°C
Soldering
Information
Dual-In-Line
Package
Soldering (10 seconds)
260
260
°C
Small
Outline
Package
Vapor Phase (60 seconds)
215
215
°C
Infrared (15 seconds)
220
220
°C
Storage temperature, T
stg
-65
150
-65
150
°C
(1)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
VALUE
UNIT
V
(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±250
V
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
Supply Voltage (V
+
- V
-
): LM124-N/LM124A/LM224-N/LM224A/LM324-N/LM324A
3
32
V
Supply Voltage (V
+
- V
-
): LM2902-N
3
26
V
Operating Input Voltage on Input pins
0
V+
V
Operating junction temperature, T
J
: LM124-N/LM124A
-55
125
°C
Operating junction temperature, T
J
: L2902-N
-40
85
°C
Operating junction temperature, T
J
: LM224-N/LM224A
-25
85
°C
Operating junction temperature, T
J
: LM324-N/LM324A
0
70
°C
5
SNOSC16D - MARCH 2000 - REVISED JANUARY 2015
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(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report,
6.4 Thermal Information
THERMAL METRIC
(1)
LM124-N /
LM224-N
LM324-N /
LM2902-N
UNIT
J/CDIP
D/SOIC
14 PINS
14 PINS
R
ΘJA
Junction-to-ambient thermal resistance
88
88
°C/W
(1)
These specifications are limited to
-55 °C ≤ T
A
≤ +125 °C for the LM124-N/LM124A. With the LM224-N/LM224A, all temperature
specifications are limited to
-25 °C ≤ T
A
≤ +85 °C, the LM324-N/LM324A temperature specifications are limited to 0 °C ≤ T
A
≤ +70 °C, and
the LM2902-N specifications are limited to
-40 °C ≤ T
A
≤ +85 °C.
(2)
V
O
•‰ 1.4V, R
S
= 0
Ω with V
+
from 5 V to 30 V; and over the full input common-mode range (0 V to V
+
- 1.5 V) for LM2902-N, V
+
from 5
V to 26 V.
(3)
The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the
state of the output so no loading change exists on the input lines.
(4)
The input common-mode voltage of either input signal voltage should not be allowed to go negative by more than 0.3 V (at 25 °C). The
upper end of the common-mode voltage range is V
+
- 1.5 V (at 25 °C), but either or both inputs can go to 32 V without damage (26 V for
LM2902-N), independent of the magnitude of V
+
.
(5)
Due to proximity of external components, insure that coupling is not originating via stray capacitance between these external parts. This
typically can be detected as this type of capacitance increases at higher frequencies.
(6)
Short circuits from the output to V
+
can cause excessive heating and eventual destruction. When considering short circuits to ground,
the maximum output current is approximately 40 mA independent of the magnitude of V
+
. At values of supply voltage in excess of 15 V,
continuous short-circuits can exceed the power dissipation ratings and cause eventual destruction. Destructive dissipation can result
from simultaneous shorts on all amplifiers.
6.5 Electrical Characteristics: LM124A/224A/324A
V
+
= 5.0 V,
(1)
, unless otherwise stated
PARAMETER
TEST CONDITIONS
LM124A
LM224A
LM324A
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
Input Offset Voltage
T
A
= 25 °C
(2)
1
2
1
3
2
3
mV
Input Bias Current
(3)
I
IN(+)
or I
IN(
-)
, V
CM
= 0 V,
T
A
= 25 °C
20
50
40
80
45
100
nA
Input Offset Current
I
IN(+)
or I
IN(
-)
, V
CM
= 0 V,
T
A
= 25 °C
2
10
2
15
5
30
nA
Input Common-Mode
Voltage Range
(4)
V
+
= 30 V, (LM2902-N,
V
+
= 26 V), T
A
= 25 °C
0
V
+
-1.5
0
V
+
-1.5
0
V
+
-1.5
V
Supply Current
Over Full Temperature Range,
R
L
=
•ž On All Op Amps
V
+
= 30 V (LM2902-N V
+
= 26 V)
1.5
3
1.5
3
1.5
3
mA
V
+
= 5 V
0.7
1.2
0.7
1.2
0.7
1.2
Large Signal
Voltage Gain
V
+
= 15 V, R
L
≥ 2 kΩ¦,
(V
O
= 1 V to 11 V), T
A
= 25 °C
50
100
50
100
25
100
V/mV
Common-Mode
Rejection Ratio
DC, V
CM
= 0 V to V
+
- 1.5 V,
T
A
= 25 °C
70
85
70
85
65
85
dB
Power Supply
Rejection Ratio
V
+
= 5 V to 30 V, (LM2902-N,
V
+
= 5V to 26 V),
T
A
= 25 °C
65
100
65
100
65
100
dB
Amplifier-to-Amplifier
Coupling
(5)
f = 1 kHz to 20 kHz, T
A
= 25 °C,
(Input Referred)
-120
-120
-120
dB
Output
Current
Source
V
IN
+
= 1 V, V
IN
-
= 0 V,
V
+
= 15 V, V
O
= 2 V, T
A
= 25 °C
20
40
20
40
20
40
mA
Sink
V
IN
-
= 1 V, V
IN
+
= 0 V,
V
+
= 15 V, V
O
= 2 V, T
A
= 25 °C
10
20
10
20
10
20
μA
V
IN
-
= 1 V, V
IN
+
= 0 V,
V
+
= 15 V, V
O
= 200 mV, T
A
= 25 °C
12
50
12
50
12
50
Short Circuit to Ground
V
+
= 15 V,
T
A
= 25 °C
(6)
40
60
40
60
40
60
mA
Input Offset Voltage
See
(2)
4
4
5
mV
V
OS
Drift
R
S
= 0
Ω
7
20
7
20
7
30
μV/ °C
Input Offset Current
I
IN(+)
- I
IN(
-)
, V
CM
= 0 V
30
30
75
nA
6
,
SNOSC16D - MARCH 2000 - REVISED JANUARY 2015
Product Folder Links:
Copyright © 2000-2015, Texas Instruments Incorporated
Electrical Characteristics: LM124A/224A/324A (continued)
V
+
= 5.0 V,
unless otherwise stated
PARAMETER
TEST CONDITIONS
LM124A
LM224A
LM324A
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
I
OS
Drift
R
S
= 0
Ω
10
200
10
200
10
300
pA/ °C
Input Bias Current
I
IN(+)
or I
IN(
-)
40
100
40
100
40
200
nA
Input Common-Mode
Voltage Range
(4)
V
+
= 30 V,
(LM2902-N, V
+
= 26 V)
0
V
+
-2
0
V
+
-2
0
V
+
-2
V
Large Signal
Voltage Gain
V
+
= 15 V (V
O
Swing = 1 V to 11 V),
R
L
≥ 2 kΩ
25
25
15
V/mV
Output
Voltage
Swing
V
OH
V
+
= 30 V
(LM2902-N,
V
+
= 26 V)
R
L
= 2 k
Ω
26
26
26
V
R
L
= 10 k
Ω
27
28
27
28
27
28
V
OL
V
+
= 5 V, R
L
= 10 k
Ω
5
20
5
20
5
20
mV
Output
Current
Source
V
O
= 2 V
V
IN
+
= +1V,
V
IN
-
= 0V,
V
+
= 15V
10
20
10
20
10
20
mA
Sink
V
IN
-
= +1V,
V
IN
+
= 0V,
V
+
= 15V
10
15
5
8
5
8
(1)
These specifications are limited to
-55 °C ≤ T
A
≤ +125 °C for the LM124-N/LM124A. With the LM224-N/LM224A, all temperature
specifications are limited to
-25 °C ≤ T
A
≤ +85 °C, the LM324-N/LM324A temperature specifications are limited to 0 °C ≤ T
A
≤ +70 °C, and
the LM2902-N specifications are limited to
-40 °C ≤ T
A
≤ +85 °C.
(2)
V
O
•‰ 1.4V, R
S
= 0
Ω with V
+
from 5 V to 30 V; and over the full input common-mode range (0 V to V
+
- 1.5 V) for LM2902-N, V
+
from 5
V to 26 V.
(3)
The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the
state of the output so no loading change exists on the input lines.
(4)
The input common-mode voltage of either input signal voltage should not be allowed to go negative by more than 0.3 V (at 25 °C). The
upper end of the common-mode voltage range is V
+
- 1.5 V (at 25 °C), but either or both inputs can go to 32 V without damage (26 V for
LM2902-N), independent of the magnitude of V
+
.
(5)
Due to proximity of external components, insure that coupling is not originating via stray capacitance between these external parts. This
typically can be detected as this type of capacitance increases at higher frequencies.
6.6 Electrical Characteristics: LM124-N/224-N/324-N/2902-N
V
+
= +5.0V,
(1)
, unless otherwise stated
PARAMETER
TEST CONDITIONS
LM124-N / LM224-N
LM324-N
LM2902-N
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
Input Offset Voltage
T
A
= 25 °C
(2)
2
5
2
7
2
7
mV
Input Bias Current
(3)
I
IN(+)
or I
IN(
-)
, V
CM
= 0 V, T
A
= 25 °C
45
150
45
250
45
250
nA
Input Offset Current
I
IN(+)
or I
IN(
-)
, V
CM
= 0 V, T
A
= 25 °C
3
30
5
50
5
50
nA
Input Common-Mode Voltage
Range
(4)
V
+
= 30 V, (LM2902-N, V
+
= 26V),
T
A
= 25 °C
0
V
+
-1.
5
0
V
+
-1.
5
0
V
+
-1.
5
V
Supply Current
Over Full Temperature Range
R
L
=
•ž On All Op Amps,
V
+
= 30 V (LM2902-N V
+
= 26 V)
1.5
3
1.5
3
1.5
3
mA
V
+
= 5 V
0.7
1.2
0.7
1.2
0.7
1.2
Large Signal Voltage Gain
V
+
= 15V, R
L
≥ 2 kΩ¦,
(V
O
= 1 V to 11 V), T
A
= 25 °C
50
100
25
100
25
100
V/mV
Common-Mode Rejection
Ratio
DC, V
CM
= 0 V to V
+
- 1.5 V, T
A
= 25 °C
70
85
65
85
50
70
dB
Power Supply Rejection Ratio
V
+
= 5 V to 30 V (LM2902-N,
V
+
= 5 V to 26 V), T
A
= 25 °C
65
100
65
100
50
100
dB
Amplifier-to-Amplifier
Coupling
(5)
f = 1 kHz to 20 kHz, T
A
= 25 °C
(Input Referred)
-120
-120
-120
dB
7
SNOSC16D - MARCH 2000 - REVISED JANUARY 2015
Product Folder Links:
Copyright © 2000-2015, Texas Instruments Incorporated
Electrical Characteristics: LM124-N/224-N/324-N/2902-N (continued)
V
+
= +5.0V,
unless otherwise stated
PARAMETER
TEST CONDITIONS
LM124-N / LM224-N
LM324-N
LM2902-N
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
(6)
Short circuits from the output to V
+
can cause excessive heating and eventual destruction. When considering short circuits to ground,
the maximum output current is approximately 40 mA independent of the magnitude of V
+
. At values of supply voltage in excess of 15 V,
continuous short-circuits can exceed the power dissipation ratings and cause eventual destruction. Destructive dissipation can result
from simultaneous shorts on all amplifiers.
Output
Current
Source
V
IN
+
= 1 V, V
IN
-
= 0 V,
V
+
= 15 V, V
O
= 2 V, T
A
= 25 °C
20
40
20
40
20
40
mA
Sink
V
IN
-
= 1 V, V
IN
+
= 0 V,
V
+
= 15 V, V
O
= 2 V, T
A
= 25 °C
10
20
10
20
10
20
mA
V
IN
-
= 1 V, V
IN
+
= 0 V,
V
+
= 15 V, V
O
= 200 mV, T
A
= 25 °C
12
50
12
50
12
50
µA
Short Circuit to Ground
V
+
= 15 V, T
A
= 25 °C
(6)
40
60
40
60
40
60
mA
Input Offset Voltage
See
(2)
7
9
10
mV
V
OS
Drift
R
S
= 0
Ω
7
7
7
µV/ °C
Input Offset Current
I
IN(+)
- I
IN(
-)
, V
CM
= 0 V
100
150
45
200
nA
I
OS
Drift
R
S
= 0
Ω
10
10
10
pA/ °C
Input Bias Current
I
IN(+)
or I
IN(
-)
40
300
40
500
40
500
nA
Input Common-Mode Voltage
Range
(4)
V
+
= 30 V, (LM2902-N, V
+
= 26 V)
0
V
+
-2
0
V
+
-2
0
V
+
-2
V
Large Signal Voltage Gain
V
+
= 15 V (V
O
Swing = 1V to 11V),
R
L
≥ 2 kΩ
25
15
15
V/mV
Output
Voltage
Swing
V
OH
V
+
= 30 V (LM2902-N,
V
+
= 26 V)
R
L
= 2 k
Ω
26
26
22
V
R
L
= 10 k
Ω
27
28
27
28
23
24
V
OL
V
+
= 5 V, R
L
= 10 k
Ω
5
20
5
20
5
100
mV
Output
Current
Source
V
O
= 2 V
V
IN
+
= 1 V,
V
IN
-
= 0 V,
V
+
= 15 V
10
20
10
20
10
20
mA
Sink
V
IN
-
= 1 V,
V
IN
+
= 0 V,
V
+
= 15 V
5
8
5
8
5
8
mA
8
,
SNOSC16D - MARCH 2000 - REVISED JANUARY 2015
Product Folder Links:
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6.7 Typical Characteristics
Figure 1. Input Voltage Range
Figure 2. Input Current
Figure 3. Supply Current
Figure 4. Voltage Gain
Figure 5. Open-Loop Frequency Response
Figure 6. Common Mode Rejection Ratio
9
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Typical Characteristics (continued)
Figure 7. Voltage Follower Pulse Response
Figure 8. Voltage Follower Pulse Response (Small Signal)
Figure 9. Large Signal Frequency Response
Figure 10. Output Characteristics Current Sourcing
Figure 11. Output Characteristics Current Sinking
Figure 12. Current Limiting
10
,
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Typical Characteristics (continued)
Figure 13. Input Current (LM2902-N Only)
Figure 14. Voltage Gain (LM2902-N Only)
11
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7 Detailed Description
7.1 Overview
The LM124-N series are op amps which operate with only a single power supply voltage, have true-differential
inputs, and remain in the linear mode with an input common-mode voltage of 0 V
DC
. These amplifiers operate
over a wide range of power supply voltage with little change in performance characteristics. At 25 °C amplifier
operation is possible down to a minimum supply voltage of 2.3 V
DC
.
7.2 Functional Block Diagram
7.3 Feature Description
The LM124 provides a compelling balance of performance versus current consumption. The 700
μA of supply
current draw over the wide operating conditions with a 1-MHz gain-bandwidth and temperature compensated
bias currents makes the LM124 an effective solution for large variety of applications. The input offset voltage of 2
mV and offset current of 5 nA, along with the 45n-A bias current across a wide supply voltage means a single
design can be used in a large number of different implementations.
7.4 Device Functional Modes
Large differential input voltages can be easily accommodated and, as input differential voltage protection diodes
are not needed, no large input currents result from large differential input voltages. The differential input voltage
may be larger than V
+
without damaging the device. Protection should be provided to prevent the input voltages
from going negative more than
-0.3 V
DC
(at 25 °C). An input clamp diode with a resistor to the IC input terminal
can be used.
To reduce the power supply drain, the amplifiers have a class A output stage for small signal levels which
converts to class B in a large signal mode. This allows the amplifiers to both source and sink large output
currents. Therefore both NPN and PNP external current boost transistors can be used to extend the power
capability of the basic amplifiers. The output voltage needs to raise approximately 1 diode drop above ground to
bias the on-chip vertical PNP transistor for output current sinking applications.
For ac applications, where the load is capacitively coupled to the output of the amplifier, a resistor should be
used, from the output of the amplifier to ground to increase the class A bias current and prevent crossover
distortion.
Where the load is directly coupled, as in dc applications, there is no crossover distortion.
Capacitive loads which are applied directly to the output of the amplifier reduce the loop stability margin. Values
of 50 pF can be accommodated using the worst-case non-inverting unity gain connection. Large closed loop
gains or resistive isolation should be used if larger load capacitance must be driven by the amplifier.
12
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Device Functional Modes (continued)
The bias network of the LM124-N establishes a drain current which is independent of the magnitude of the power
supply voltage over the range of from 3 V
DC
to 30 V
DC
.
Output short circuits either to ground or to the positive power supply should be of short time duration. Units can
be destroyed, not as a result of the short circuit current causing metal fusing, but rather due to the large increase
in IC chip dissipation which will cause eventual failure due to excessive junction temperatures. Putting direct
short-circuits on more than one amplifier at a time will increase the total IC power dissipation to destructive
levels, if not properly protected with external dissipation limiting resistors in series with the output leads of the
amplifiers. The larger value of output source current which is available at 25 °C provides a larger output current
capability at elevated temperatures (see
than a standard IC op amp.
13
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Product Folder Links:
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8
Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM124 series of amplifiers is specified for operation from 3 V to 32 V ( ±1.5 V to ±16 V). Many of the
specifications apply from -40 °C to 125 °C. Parameters that can exhibit significant variance with regards to
operating voltage or temperature are presented in
8.2 Typical Applications
emphasizes operation on only a single power supply voltage. If complementary power supplies are
available, all of the standard op amp circuits can be used. In general, introducing a pseudo-ground (a bias
voltage reference of V
+
/2) will allow operation above and below this value in single power supply systems. Many
application circuits are shown which take advantage of the wide input common-mode voltage range which
includes ground. In most cases, input biasing is not required and input voltages which range to ground can easily
be accommodated.
8.2.1 Non-Inverting DC Gain (0 V Input = 0 V Output)
*R not needed due to temperature independent I
IN
Figure 15. Non-Inverting Amplifier with G=100
8.2.1.1 Design Requirements
For this example application, the required signal gain is a non-inverting 100x ±5% with a supply voltage of 5 V.
8.2.1.2 Detailed Design Procedure
Using the equation for a non-inverting gain configuration, Av = 1+R2/R1. Setting the R1 to 10 k
Ω, R2 is 99 times
larger than R1, which is 990 k
Ω. A 1MΩ is more readily available, and provides a gain of 101, which is within the
desired specification.
The gain-frequency characteristic of the amplifier and its feedback network must be such that oscillation does not
occur. To meet this condition, the phase shift through amplifier and feedback network must never exceed 180 °
for any frequency where the gain of the amplifier and its feedback network is greater than unity. In practical
applications, the phase shift should not approach 180 ° since this is the situation of conditional stability. Obviously
the most critical case occurs when the attenuation of the feedback network is zero.
14
,
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Typical Applications (continued)
8.2.1.3 Application Curve
Figure 16. Non-Inverting Amplified Response Curve
15
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Typical Applications (continued)
8.2.2 Other Application Circuits at V
+
= 5.0 V
DC
Where: V
0
= V
1
+ V
2
- V
3
- V
4
(V
1
+ V
2
)
≥ (V
3
+ V
4
) to keep V
O
> 0 V
DC
Where: V
0
= 0 V
DC
for V
IN
= 0 V
DC
A
V
= 10
Figure 17. DC Summing Amplifier
(V
IN'S
≥ 0 V
DC
And V
O
≥ V
DC
)
Figure 18. Power Amplifier
f
o
= 1 kHz
Q = 50
A
V
= 100 (40 dB)
Figure 19. LED Driver
Figure 20. †śBI-QUAD†ť RC Active Bandpass Filter
16
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Product Folder Links:
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Typical Applications (continued)
Figure 21. Fixed Current Sources
*(Increase R1 for I
L
small)
Figure 22. Lamp Driver
Figure 23. Current Monitor
Figure 24. Driving TTL
Figure 25. Voltage Follower
17
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Typical Applications (continued)
Figure 26. Pulse Generator
Figure 27. Squarewave Oscillator
I
O
= 1 amp/volt V
IN
(Increase R
E
for I
o
small)
Figure 28. Pulse Generator
Figure 29. High Compliance Current Sink
18
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Typical Applications (continued)
Figure 30. Low Drift Peak Detector
Figure 31. Comparator With Hysteresis
V
O
= V
R
*Wide control voltage range:
0 V
DC
≤ V
C
≤ 2 (V
+
-1.5 V
DC
)
Figure 32. Ground Referencing a Differential Input
Signal
Figure 33. Voltage Controlled Oscillator Circuit
19
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Typical Applications (continued)
Q = 1
A
V
= 2
Figure 34. Photo Voltaic-Cell Amplifier
Figure 35. DC Coupled Low-Pass RC Active Filter
Figure 36. AC Coupled Inverting Amplifier
Figure 37. AC Coupled Non-Inverting Amplifier
20
,
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Typical Applications (continued)
Figure 38. High Input Z, DC Differential Amplifier
Figure 39. High Input Z Adjustable-Gain DC Instrumentation Amplifier
21
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Typical Applications (continued)
Figure 40. Bridge Current Amplifier
Figure 41. Using Symmetrical Amplifiers to Reduce Input Current (General Concept)
22
,
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Typical Applications (continued)
f
O
= 1 kHz
Q = 25
Figure 42. Bandpass Active Filter
1: VOUTA
14: VOUTD
13: IN-D
12: IN+D
11: GND
10: IN+C
9: IN-C
8: VOUTC
2: IN-A
3: IN+A
4: V+
5: IN+B
6: IN-B
7: VOUTB
2
GND
2
GND
2
GND
2
GND
2
VOUTA
2
VOUTB
2
VOUTC
2
VOUTD
2
IN+B
2
IN+A
2
IN+D
2
IN+C
1
GND
2
V+
1
IN-A
1
IN-A
1
IN-D
1
IN-D
1
IN-C
1
IN-C
1
IN-B
1
IN-B
1
VINA
1
VINB
1
VIND
1
VINC
GND
GND
GND
GND
GND
GND
V+
IN+A
IN+B
IN-B
IN-A
IN+C
VINC
IN-C
IN+D
IN-D
VOUTB
VOUTC
VOUTA
VOUTD
VOUT
A
VOUTD
VINC
VIND
GND
GND
GND
VINC
23
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Product Folder Links:
Copyright © 2000-2015, Texas Instruments Incorporated
9 Power Supply Recommendations
The pinouts of the package have been designed to simplify PC board layouts. Inverting inputs are adjacent to
outputs for all of the amplifiers and the outputs have also been placed at the corners of the package (pins 1, 7, 8,
and 14).
Precautions should be taken to insure that the power supply for the integrated circuit never becomes reversed in
polarity or that the unit is not inadvertently installed backwards in a test socket as an unlimited current surge
through the resulting forward diode within the IC could cause fusing of the internal conductors and result in a
destroyed unit.
10 Layout
10.1 Layout Guidelines
The V + pin should be bypassed to ground with a low-ESR capacitor. The optimum placement is closest to the V
+ and ground pins.
Take care to minimize the loop area formed by the bypass capacitor connection between V + and ground.
The ground pin should be connected to the PCB ground plane at the pin of the device.
The feedback components should be placed as close to the device as possible minimizing strays.
10.2 Layout Example
Figure 43. Layout Example
24
,
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Product Folder Links:
Copyright © 2000-2015, Texas Instruments Incorporated
11 Device and Documentation Support
11.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
LM124-N
LM224-N
LM2902-N
LM324-N
11.2 Trademarks
All trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
— TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
PACKAGE OPTION ADDENDUM
www.ti.com
19-Mar-2015
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp ( °C)
Device Marking
(4/5)
Samples
LM124AJ/PB
ACTIVE
CDIP
J
14
25
TBD
Call TI
Call TI
LM124AJ
LM124J/PB
ACTIVE
CDIP
J
14
25
TBD
Call TI
Call TI
LM124J
LM224J
ACTIVE
CDIP
J
14
25
TBD
Call TI
Call TI
-25 to 85
LM224J
LM2902M
NRND
SOIC
D
14
55
TBD
Call TI
Call TI
-40 to 85
LM2902M
LM2902M/NOPB
ACTIVE
SOIC
D
14
55
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LM2902M
LM2902MT
NRND
TSSOP
PW
14
94
TBD
Call TI
Call TI
-40 to 85
LM290
2MT
LM2902MT/NOPB
ACTIVE
TSSOP
PW
14
94
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LM290
2MT
LM2902MTX/NOPB
ACTIVE
TSSOP
PW
14
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LM290
2MT
LM2902MX
NRND
SOIC
D
14
2500
TBD
Call TI
Call TI
-40 to 85
LM2902M
LM2902MX/NOPB
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LM2902M
LM2902N/NOPB
ACTIVE
PDIP
NFF
14
25
Green (RoHS
& no Sb/Br)
CU SN
Level-1-NA-UNLIM
-40 to 85
LM2902N
LM324AM
NRND
SOIC
D
14
55
TBD
Call TI
Call TI
0 to 70
LM324AM
LM324AM/NOPB
ACTIVE
SOIC
D
14
55
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
0 to 70
LM324AM
LM324AMX
NRND
SOIC
D
14
2500
TBD
Call TI
Call TI
0 to 70
LM324AM
LM324AMX/NOPB
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
0 to 70
LM324AM
LM324AN/NOPB
ACTIVE
PDIP
NFF
14
25
Green (RoHS
& no Sb/Br)
CU SN
Level-1-NA-UNLIM
0 to 70
LM324AN
LM324J
ACTIVE
CDIP
J
14
25
TBD
Call TI
Call TI
0 to 70
LM324J
LM324M
NRND
SOIC
D
14
55
TBD
Call TI
Call TI
0 to 70
LM324M
LM324M/NOPB
ACTIVE
SOIC
D
14
55
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
0 to 70
LM324M
LM324MT/NOPB
ACTIVE
TSSOP
PW
14
94
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
0 to 70
LM324
MT
PACKAGE OPTION ADDENDUM
www.ti.com
19-Mar-2015
Addendum-Page 2
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp ( °C)
Device Marking
(4/5)
Samples
LM324MTX
NRND
TSSOP
PW
14
2500
TBD
Call TI
Call TI
0 to 70
LM324
MT
LM324MTX/NOPB
ACTIVE
TSSOP
PW
14
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
0 to 70
LM324
MT
LM324MX
NRND
SOIC
D
14
2500
TBD
Call TI
Call TI
0 to 70
LM324M
LM324MX/NOPB
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
0 to 70
LM324M
LM324N/NOPB
ACTIVE
PDIP
NFF
14
25
Green (RoHS
& no Sb/Br)
CU SN
Level-1-NA-UNLIM
0 to 70
LM324N
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
PACKAGE OPTION ADDENDUM
www.ti.com
19-Mar-2015
Addendum-Page 3
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package
Type
Package
Drawing
Pins
SPQ
Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
LM2902MTX/NOPB
TSSOP
PW
14
2500
330.0
12.4
6.95
5.6
1.6
8.0
12.0
Q1
LM2902MX
SOIC
D
14
2500
330.0
16.4
6.5
9.35
2.3
8.0
16.0
Q1
LM2902MX/NOPB
SOIC
D
14
2500
330.0
16.4
6.5
9.35
2.3
8.0
16.0
Q1
LM324AMX
SOIC
D
14
2500
330.0
16.4
6.5
9.35
2.3
8.0
16.0
Q1
LM324AMX/NOPB
SOIC
D
14
2500
330.0
16.4
6.5
9.35
2.3
8.0
16.0
Q1
LM324MTX
TSSOP
PW
14
2500
330.0
12.4
6.95
5.6
1.6
8.0
12.0
Q1
LM324MTX/NOPB
TSSOP
PW
14
2500
330.0
12.4
6.95
5.6
1.6
8.0
12.0
Q1
LM324MX
SOIC
D
14
2500
330.0
16.4
6.5
9.35
2.3
8.0
16.0
Q1
LM324MX/NOPB
SOIC
D
14
2500
330.0
16.4
6.5
9.35
2.3
8.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Nov-2015
Pack Materials-Page 1
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM2902MTX/NOPB
TSSOP
PW
14
2500
367.0
367.0
35.0
LM2902MX
SOIC
D
14
2500
367.0
367.0
35.0
LM2902MX/NOPB
SOIC
D
14
2500
367.0
367.0
35.0
LM324AMX
SOIC
D
14
2500
367.0
367.0
35.0
LM324AMX/NOPB
SOIC
D
14
2500
367.0
367.0
35.0
LM324MTX
TSSOP
PW
14
2500
367.0
367.0
35.0
LM324MTX/NOPB
TSSOP
PW
14
2500
367.0
367.0
35.0
LM324MX
SOIC
D
14
2500
367.0
367.0
35.0
LM324MX/NOPB
SOIC
D
14
2500
367.0
367.0
35.0
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Nov-2015
Pack Materials-Page 2
MECHANICAL DATA
N0014A
www.ti.com
N14A (Rev G)
NFF0014A
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as †ścomponents†ť) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
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