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MAXQ3108 -- Chipset Eliminates Costly Current Transformers in Polyphase Energy Meters
 
 
 


Maxim Integrated Products (NASDAQ: MXIM) introduces a new chipset, the MAXQ3108 and DS8102, that reduces the bill of materials (BOM) cost of a polyphase energy meter. Together, the MAXQ3108 and DS8102 replace three high-cost current transformers with three low-cost shunts to save both cost and space.

The MAXQ3108 is a low-power microcontroller that features two high-performance MAXQ20 cores: a dedicated core (DSPCore) for intensive data processing and a user core (UserCore) for supervisory functions. The two cores can operate at different clock speeds, allowing lower system power consumption for even processing intensive applications. The UserCore can be configured to run at the lowest clock rate possible for monitoring the peripherals for communication activities, while the DSPCore runs at the highest speed. Each core has access to an independent math accelerator (a multiply/accumulate unit). The UserCore supports SPI™, I²C, two UART channels with one channel supporting IR carrier modulation, a trimmable real-time clock (RTC), battery-backed RTC registers, and data memory. The DSPCore is fully user programmable and configurable. With the standard 32,768Hz crystal, the DSPCore operates at 10.027MHz, while the UserCore runs at 5.014MHz.
Key Features
  • High-Performance, Low-Power, Dual 16-Bit RISC Cores
  • Approaches 1MIPS per MHz
  • System Clock
    • 10.027MHz (DSPCore)
    • 5.014MHz (UserCore)
  • 33 Instructions
  • Approximately 100ns Execution Time at 10.027MHz
  • Three Independent Data Pointers Accelerate Data Movement with Automatic Increment/Decrement
  • 16-Bit Instruction Word, 16-Bit Data Bus
  • 16 x 16-Bit General-Purpose Working Registers for Each Core
  • 16-Level Hardware Stack for Each Core
  • Hardware Support for Software Stack
  • Memory Features
    • UserCore
      • 64KB Flash Program Memory
      • 16B Battery-Backed (VBAT) Data SRAM
      • 4KB Utility ROM
      • 2KB Data SRAM; 10KB Total Data SRAM (If DSPCore Inactive)
    • DSPCore
      • 8KB User-Loadable SRAM Code Memory
      • 1KB Data SRAM
  • Peripherals
    • FLL (10MHz Output with 32kHz Input)
    • SPI Master, I²C Master
    • Two UART Channels (One Supports IR Carrier Modulation)
    • Math Accelerator for Each Core
    • Three Manchester Decoder and Cubic Sinc Filter Channels for Interfacing to DS8102 Delta-Sigma Modulators
    • Two 16-Bit Programmable Timer/Counters
    • RTC with Alarms and Digital Trim, Dedicated Battery-Backup Pin (VBAT)
    • Two Programmable Pulse Generators
    • Independent Watchdog Timer for Each Core
    • External Interrupts
    • JTAG Interface
  • Operating Modes
    • Stop Mode: 0.1µA typ
    • Active Current at 10MHz and VDD = 2.0V: 1.0mA typ


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Publicada el 23 de Mar de 2009 - 12:56 PM   

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