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Atmel-3408K-SEEPROM-AT93C86A-Datasheet_122015
Features
Low-voltage Operation
̶
V
CC
= 1.8V to 5.5V
̶
V
CC
= 2.7V to 5.5V
User-selectable Internal Organization
̶
16K: 2,048 x 8 or 1,024 x 16
3-wire Serial Interface
Sequential Read Operation
Schmitt Trigger, Filtered Inputs for Noise Suppression
2MHz Clock Rate (5V)
Self-timed Write Cycle (10ms Max)
High Reliability
̶
Endurance: 1,000,000 Write Cycles
̶
Data Retention: 100 Years
8-lead JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN, and 8-lead PDIP Packages
Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers
Description
The Atmel
AT93C86A provides 16,384 bits of Serial Electrically Erasable
Programmable Read-Only Memory (EEPROM) organized as 1,024 words of 16
bits each (when the ORG pin is connected to V
CC
) and 2,048 words of 8 bits each
(when the ORG pin is tied to ground). The device is optimized for use in many
industrial and commercial applications where low-power and low-voltage
operations are essential. The AT93C86A is available in space-saving 8-lead
JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN, and 8-lead PDIP packages.
The AT93C86A is enabled through the Chip Select pin (CS) and accessed via a
3-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift
Clock (SK). Upon receiving a Read instruction at DI, the address is decoded, and
the data is clocked out serially on the DO pin. The write cycle is completely
self-timed, and no separate erase cycle is required before Write. The write cycle is
only enabled when the part is in the Erase/Write Enable state. When CS is
brought high following the initiation of a write cycle, the DO pin outputs the
Ready/Busy status of the part.
The AT93C86A operates from 1.8V to 5.5V or from
2.7V to 5.5V
.
AT93C86A
3-wire Serial EEPROM
16K (2,048 x 8 or 1,024 x 16)
DATASHEET
AT93C86A [DATASHEET]
Atmel-3408K-SEEPROM-AT93C86A-Datasheet_122015
2
1.
Pin Configurations and Pinouts
Table 1-1.
Pin Configurations
2.
Absolute Maximum Ratings*
Pin Name
Function
CS
Chip Select
SK
Serial Data Clock
DI
Serial Data Input
DO
Serial Data Output
GND
Ground
V
CC
Power Supply
ORG
Internal Organization
NC
No Connect
8-lead TSSOP
(Top View)
1
2
3
4
8
7
6
5
CS
SK
DI
DO
V
CC
NC
ORG
GND
1
2
3
4
CS
SK
DI
DO
8
7
6
5
V
CC
NC
ORG
GND
8-lead SOIC
(Top View)
1
2
3
4
CS
SK
DI
DO
8
7
6
5
V
CC
NC
ORG
GND
8-pad UDFN
(Top View)
8-lead PDIP
(Top View)
CS
SK
DI
DO
V
CC
NC
ORG
GND
1
2
3
4
8
7
6
5
Note: Drawings are not to scale.
Operating Temperature . . . . . . . . . . .-55
C to +125C
Storage Temperature . . . . . . . . . . . . .-65
C to +150C
Voltage on any pin
with respect to ground . . . . . . . . . . . -1.00V to +7.00V
Maximum Operating Voltage . . . . . . . . . . . . . . . 6.25V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . .5.0mA
*Notice: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. This is a stress rating only, and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
3
AT93C86A [DATASHEET]
Atmel-3408K-SEEPROM-AT93C86A-Datasheet_122015
3.
Block Diagram
Figure 3-1.
Block Diagram
Note:
When the ORG pin is connected to V
CC
, the x16 organization is selected. When it is connected to ground,
the x8 organization is selected. If the ORG pin is left unconnected, and the application does not load the input
beyond the capability of the internal 1M
Ω
pull-up resistor, then the x16 organization is selected.
ORG
DI
CS
SK
V
CC
GND
Address
Decoder
Output
Buffer
Data
Register
Mode Decode
Logic
Clock
Generator
DO
Memory Array
2,048 x 8
or
1,024 x 16
AT93C86A [DATASHEET]
Atmel-3408K-SEEPROM-AT93C86A-Datasheet_122015
4
4.
Memory Organization
4.1
Pin Capacitance
Table 4-1.
Pin Capacitance
Note:
1.
This parameter is characterized, and is not 100% tested.
4.2
DC Characteristics
Table 4-2.
DC Characteristics
Note:
1.
V
IL
min and V
IH
max are reference only, and are not tested.
Applicable over recommended operating range from T
A
= 25
C, f = 1.0MHz, V
CC
= 5.0V (unless otherwise noted).
Symbol
Test Conditions
Max
Units
Conditions
C
OUT
Output Capacitance (DO)
5
pF
V
OUT
= 0V
C
IN
Input Capacitance (CS, SK, DI)
5
pF
V
IN
= 0V
Applicable over recommended operating range from T
AI
= -40 C to +85 C, V
CC
= 1.8V to 5.5V (unless otherwise noted).
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
V
CC1
Supply Voltage
1.8
5.5
V
V
CC2
Supply Voltage
2.7
5.5
V
V
CC3
Supply Voltage
4.5
5.5
V
I
CC
Supply Current
V
CC
= 5.0V
Read at 1.0MHz
0.5
2.0
mA
Write at 1.0MHz
0.5
2.0
mA
I
SB1
Standby Current
V
CC
= 1.8V
CS = 0V
0.4
1.0
μA
I
SB2
Standby Current
V
CC
= 2.7V
CS = 0V
6.0
10.0
μA
I
SB3
Standby Current
V
CC
= 5.0V
CS = 0V
10.0
15.0
μA
I
IL
Input Leakage
V
IN
= 0V to V
CC
0.1
3.0
μA
I
OL
Output Leakage
V
IN
= 0V to V
CC
0.1
3.0
μA
V
IL1
Input Low Voltage
2.7V
V
CC
5.5V
0.6
0.8
V
V
IH1
Input High Voltage
2.7V
V
CC
5.5V
2.0
V
CC
+ 1
V
V
IL2
Input Low Voltage
1.8V
V
CC
2.7V
0.6
V
CC
x 0.3
V
V
IH2
Input High Voltage
1.8V
V
CC
2.7V
V
CC
x 0.7
V
CC
+ 1
V
V
OL1
Output Low Voltage
2.7V
V
CC
5.5V
I
OL
= 2.1mA
0.4
V
V
OH1
Output High Voltage
2.7V
V
CC
5.5V
I
OH
=
0.4mA
2.4
V
V
OL2
Output Low Voltage
1.8V
V
CC
2.5V
I
OL
= 0.15mA
0.2
V
V
OH2
Output High Voltage
1.8V
V
CC
2.7V
I
OH
=
100μA
V
CC
0.2
V
5
AT93C86A [DATASHEET]
Atmel-3408K-SEEPROM-AT93C86A-Datasheet_122015
4.3
AC Characteristics
Table 4-3.
AC Characteristics
Note:
1.
This parameter is characterized, and is not 100% tested.
Applicable over recommended operating range from T
AI
= -40 C to + 85 C, CL = 1 TTL gate and 100pF (unless otherwise
noted).
Symbol
Parameter
Test Condition
Min
Typ
Max
Units
f
SK
SK Clock Frequency
4.5V
V
CC
5.5V
0
2
MHz
2.7V
V
CC
5.5V
0
1
MHz
1.8V
V
CC
5.5V
0
250
kHz
t
SKH
SK High Time
2.7V
V
CC
5.5V
250
ns
1.8V
V
CC
5.5V
1000
ns
t
SKL
SK Low Time
2.7V
V
CC
5.5V
250
ns
1.8V
V
CC
5.5V
1000
ns
t
CS
Minimum CS Low Time
2.7V
V
CC
5.5V
250
ns
1.8V
V
CC
5.5V
1000
ns
t
CSS
CS Setup Time
Relative to SK
2.7V
V
CC
5.5V
50
ns
1.8V
V
CC
5.5V
200
ns
t
DIS
DI Setup Time
Relative to SK
2.7V
V
CC
5.5V
100
ns
1.8V
V
CC
5.5V
400
ns
t
CSH
CS Hold Time
Relative to SK
0
ns
t
DIH
DI Hold Time
Relative to SK
2.7V
V
CC
5.5V
100
ns
1.8V
V
CC
5.5V
400
ns
t
PD1
Output Delay to 1
AC Test
2.7V
V
CC
5.5V
250
ns
1.8V
V
CC
5.5V
1000
ns
t
PD0
Output Delay to 0
AC Test
2.7V
V
CC
5.5V
250
ns
1.8V
V
CC
5.5V
1000
ns
t
SV
CS to Status Valid
AC Test
2.7V
V
CC
5.5V
250
ns
1.8V
V
CC
5.5V
1000
ns
t
DF
CS to DO in
High-impedance
AC Test
2.7V
V
CC
5.5V
150
ns
CS = V
IL
1.8V
V
CC
5.5V
400
ns
t
WP
Write Cycle Time
1.8V
V
CC
5.5V
0.1
3
10
ms
Endurance
5.0V, 25 C
1,000,000
Write
Cycles
AT93C86A [DATASHEET]
Atmel-3408K-SEEPROM-AT93C86A-Datasheet_122015
6
5.
Functional Description
The AT93C86A is accessed via a simple and versatile 3-wire serial communication interface. Device operation
is controlled by seven instructions issued by the Host processor. A valid instruction starts with a rising edge of
CS and consists of a Start bit (Logic 1), followed by the appropriate opcode, and the desired memory address
location.
Table 5-1.
AT93C86A Instruction Set
Note:
1.
The X in the address field represent dont care values, and must be clocked.
READ: The READ instruction contains the address code for the memory location to be read. After the
instruction and address are decoded, data from the selected memory location is available at the Serial Output
pin, DO. Output data changes are synchronized with the rising edges of the Serial Clock pin, SK. It should be
noted that a dummy bit (Logic 0) precedes the 8-bit or 16-bit data output string. The AT93C86A supports
sequential Read operations. The device will automatically increment the internal address pointer and clock out
the next memory location as long as Chip Select (CS) is held high. In this case, the dummy bit (Logic 0) will not
be clocked out between memory locations, thus allowing for a continuous stream of data to be read.
Erase/Write Enable (EWEN): To ensure data integrity, the part automatically goes into the Erase/Write Disable
(EWDS) state when power is first applied. An Erase/Write Enable (EWEN) instruction must be executed first
before any programming instructions can be carried out.
Note: Once in the EWEN state, programming remains enabled until an EWDS instruction is executed, or V
CC
power is removed from the part.
Instruction
SB
Opcode
Address
Data
Comments
x8
x16
x8
x16
READ
1
10
A
10
- A
0
A
9
- A
0
Reads data stored in memory at
specified address.
EWEN
1
00
11XXXXXXX
11XXXXXX
Write Enable must precede all
programming modes.
ERASE
1
11
A
10
- A
0
A
9
- A
0
Erases memory location A
N
- A
0
.
WRITE
1
01
A
10
- A
0
A
9
- A
0
D
7
- D
0
D
15
- D
0
Writes memory location A
N
- A
0
.
ERAL
1
00
10XXXXXXX
10XXXXXX
Erases all memory locations.
Valid only at V
CC
= 4.5V to 5.5V.
WRAL
1
00
01XXXXXXX
01XXXXXX
D
7
- D
0
D
15
- D
0
Writes all memory locations.
Valid only at V
CC
= 4.5V to 5.5V and
Disable Register cleared.
EWDS
1
00
00XXXXXXX
00XXXXXX
Disables all programming
instructions.
7
AT93C86A [DATASHEET]
Atmel-3408K-SEEPROM-AT93C86A-Datasheet_122015
ERASE: The ERASE instruction programs all bits in the specified memory location to the Logic 1 state. The
self-timed erase cycle starts once the ERASE instruction and address are decoded. The DO pin outputs the
Ready/Busy status of the part if CS is brought high after being kept low for a minimum of t
CS
. A Logic 1 at the
DO pin indicates that the selected memory location has been erased, and the part is ready for another
instruction.
WRITE: The WRITE instruction contains the 8-bits or 16-bits of data to be written into the specified memory
location. The self-timed programming cycle, t
WP
, starts after the last bit of data is received at Serial Data Input
pin DI. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a
minimum of t
CS
. A Logic 0 at DO indicates that programming is still in progress. A Logic 1 indicates that the
memory location at the specified address has been written with the data pattern contained in the instruction, and
the part is ready for further instructions. A Ready/Busy status cannot be obtained if CS is brought high after the
end of the self-timed programming cycle, t
WP
.
Erase All (ERAL): The Erase All (ERAL) instruction programs every bit in the Memory Array to the Logic 1 state
and is primarily used for testing purposes. The DO pin outputs the ready/busy status of the part if CS is brought
high after being kept low for a minimum of t
CS
. The ERAL instruction is valid only at
V
CC
= 5.0V 10%
.
Write All (WRAL): The Write All (WRAL) instruction programs all memory locations with the data patterns
specified in the instruction. The DO pin outputs the Ready/Busy status of the part if CS is brought high after
being kept low for a minimum of t
CS
. The WRAL instruction is valid only at
V
CC
= 5.0V 10%.
Erase/Write Disable (EWDS): To protect against accidental data disturbance, the Erase/Write Disable (EWDS)
instruction disables all programming modes and should be executed after all programming operations. The
operation of the Read instruction is independent of both the EWEN and EWDS instructions and can be
executed at any time.
AT93C86A [DATASHEET]
Atmel-3408K-SEEPROM-AT93C86A-Datasheet_122015
8
6.
Timing Diagrams
Figure 6-1.
Synchronous Data Timing
Note:
1.
This is the minimum SK period.
Table 6-1.
Organization Key for Timing Diagrams
Figure 6-2.
ERASE Timing
I/O
AT93C86A (16K)
x8
x16
A
N
A
10
A
9
D
N
D
7
D
15
CS
SK
DI
DO (Read)
DO (Program)
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
V
OL
Status Valid
t
CSS
t
DIS
t
SV
t
DIH
t
PD0
t
SKH
t
SKL
t
PD1
t
CSH
t
DF
t
DF
1 s
(1)
CS
SK
DI
DO
High-impedance
High-impedance
1
1
...
1
AN
t
CS
t
SV
t
DF
t
WP
AN-1 AN-2
A0
Check
Status
Standby
Ready
Busy
9
AT93C86A [DATASHEET]
Atmel-3408K-SEEPROM-AT93C86A-Datasheet_122015
Figure 6-3.
READ Timing
Figure 6-4.
EWEN Timing
Figure 6-5.
WRITE Timing
High-impedance
CS
SK
DI
DO
1 1
0
AN
A0
0
DN
D0
t
CS
1
0
0
1
1
...
CS
SK
DI
t
CS
CS
SK
DI
t
CS
t
WP
1
1
AN
DN
0
A0
D0
...
...
DO
High-impedance
Busy
Ready
AT93C86A [DATASHEET]
Atmel-3408K-SEEPROM-AT93C86A-Datasheet_122015
10
Figure 6-6.
ERAL Timing
Note:
1.
V
CC
= 4.5V to 5.5V.
Figure 6-7.
Note:
1.
Valid only at V
CC
= 4.5V to 5.5V.
Figure 6-8.
EWDS Timing
CS
SK
DI
DO
High-impedance
High-impedance
CS
SK
DI
DO
1
1
0
0
0
Ready
Busy
Check
Status
Standby
t
WP
t
CS
t
SV
t
DF
CS
SK
DI
DO
High-impedance
Busy
Ready
1
0
0
1
...
DN
t
CS
t
WP
...
D0
0
CS
SK
DI
DO
1
0
0
0
0
...
CS
SK
DI
t
CS
11
AT93C86A [DATASHEET]
Atmel-3408K-SEEPROM-AT93C86A-Datasheet_122015
7.
Ordering Code Detail
A T 9 3 C 8 6 A N - 1 0 S U - 1 . 8 - E
Atmel Designator
Product Family
Device Density
Device Revision
Operating Voltage
Package Type
86 = 16-Kilobit
1.8 or 18 = 1.8V to 5.5V
2.7 = 2.7V to 5.5V
Package Device Grade
S =
JEDEC
SOIC
T =
TSSOP
Y =
UDFN
P =
PDIP
Shipping Carrier Option
Blank = Tape and Reel, Standard Quantity Option
E = Tape and Reel, Expanded Quantity Option
93C = Microwire-Compatible
3-Wire Serial EEPROM
Package Variation
(Package Type Dependent)
N = 0.150 width SOIC
Y6 = 2.0x3.0mm body UDFN
Speed Type
10 = Default value
Note: This field is not used for
Serial EEPROM products.
U = Green, Matte Tin Lead Finish
or SnAgCu Ball
Industrial Temperature Range
(-40 C to +85 C)
H = Green, NiPdAu Lead Finish
Industrial Temperature Range
(-40 C to +85 C)
11 = 11mil Wafer Thickness
AT93C86A [DATASHEET]
Atmel-3408K-SEEPROM-AT93C86A-Datasheet_122015
12
8.
Part Markings
DRAWING NO.
REV.
TITLE
93C86ASM
A
6/11/14
93C86ASM, AT93C86A Package Marking Information
Package Mark Contact:
DL-CSO-Assy_eng@atmel.com
SU%%
93C86A
ATMELYWW
8-lead SOIC
8-lead TSSOP
AT###
U%
8-pad UDFN
###
H%
YXX
2.0 x 3.0 mm Body
Note 2: Package drawings are not to scale
Note 1: designates pin 1
AT93C86A: Package Marking Information
Catalog Number Truncation
AT93C86A
Truncation Code ###: 86A
Date
Codes
Voltages
Y = Year
M = Month
WW = Work Week of Assembly
% = Minimum Voltage
4: 2014
8: 2018
A: January
02: Week 2
3 or 27: 2.7V min
5: 2015
9: 2019
B: February
04: Week 4
1 or 18: 1.8V min
6: 2016
0: 2020
...
...
7: 2017
1: 2021
L: December
52: Week 52
Country of Assembly
Lot Number
Grade/Lead Finish Material
@ = Country of Assembly
AAA...A = Atmel Wafer Lot Number
H: Industrial/NiPdAu
U: Industrial/Matte Tin/SnAgCu
Trace
Code
Atmel Truncation
XX = Trace Code (Atmel Lot Numbers Correspond to Code)
AT: Atmel
Example: AA, AB.... YZ, ZZ
ATM: Atmel
ATML: Atmel
Note: Lot Number and location of assembly
on the bottom side of the package.
Note: Lot Number, location of assembly and
YWW date code on the bottom side of
the package.
PU%%
93C86A
ATMLUYWW
8-lead PDIP
Note: Lot Number and location of assembly
on the bottom side of the package.
13
AT93C86A [DATASHEET]
Atmel-3408K-SEEPROM-AT93C86A-Datasheet_122015
9.
Ordering Information
Notes: 1.
and
2. For Waffle pack and Wafer form; order as SL788 for inkless Wafer form. Bumped die available upon request. Please
contact Atmel sales.
Atmel Ordering Code
Lead
Finish
Package
Voltage
Delivery Information
Operation
Range
Form
Quantity
AT93C86A-10SU-1.8
NiPdAu
Lead-free
Halogen-free
8S1
1.8V to 5.5V
Tape and Reel
4,000 per Reel
Industrial
Temperature
(-40
C to 85C)
AT93C86A-10SU-2.7
2.7V to 5.5V
Tape and Reel
4,000 per Reel
AT93C86A-10TU-1.8
8X
1.8V to 5.5V
Tape and Reel
5,000 per Reel
AT93C86A-10TU-2.7
2.7V to 5.5V
Tape and Reel
5,000 per Reel
AT93C86A-10PU-1.8
Matte Tin
Lead-free
Halogen-free
8P3
1.8V to 5.5V
Tape and Reel
4,000 per Reel
AT93C86A-10PU-2.7
2.7V to 5.5V
Tape and Reel
4,000 per Reel
AT93C86AY6-10YH-1.8
NiPdAu
Lead-free
Halogen-free
8MA2
1.8V to 5.5V
Tape and Reel
5,000 per Reel
AT93C86AY6-10YH-18-E
Tape and Reel
15,000 per Reel
AT93C86A-W1.8-11
N/A
Wafer Sale
1.8V to 5.5V
Package Type
8S1
8-lead, 0.150 wide, Plastic Gull Wing, Small Outline (JEDEC SOIC)
8X
8-lead, 0.170 wide, Thin Shrink Small Outline (TSSOP)
8P3
8-lead, 0.300 wide body, Plastic Dual In-line Package (PDIP)
8MA2
8-pad, 2.00mm x 3.00mm body, 0.50mm pitch, Ultra Thin Dual No Lead (UDFN)
AT93C86A [DATASHEET]
Atmel-3408K-SEEPROM-AT93C86A-Datasheet_122015
14
10.
Packaging Information
10.1 8S1 8-lead JEDEC SOIC
DRAWING NO.
REV.
TITLE
GPC
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
NOTE
A1
0.10
-
0.25
A
-
-
1.75
b 0.31 - 0.51
C
0.17
-
0.25
D
4.90 BSC
E
6.00 BSC
E1
3.90 BSC
e
1.27 BSC
L 0.40 - 1.27
Ø
Ø
0 - 8
Ø
E
1
N
TOP VIEW
C
E1
END VIEW
A
b
L
A1
e
D
SIDE VIEW
Package Drawing Contact:
packagedrawings@atmel.com
8S1
H
3/6/2015
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
8S1, 8-lead (0.150 Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
SWB
15
AT93C86A [DATASHEET]
Atmel-3408K-SEEPROM-AT93C86A-Datasheet_122015
10.2 8X 8-lead TSSOP
DRAWING NO.
REV.
TITLE
GPC
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
NOTE
A - -
1.20
A1 0.05 - 0.15
A2 0.80
1.00
1.05
D 2.90
3.00
3.10
2,
5
E
6.40
BSC
E1 4.30
4.40
4.50
3,
5
b
0.19
0.25
0.30
4
e
0.65 BSC
L
0.45
0.60
0.75
L1
1.00
REF
C 0.09 -
0.20
Side View
End View
Top View
A2
A
L
L1
D
1
E1
N
b
Pin 1 indicator
this corner
E
e
Notes:
1. This drawing is for general information only.
Refer to JEDEC Drawing MO-153, Variation AA, for proper
dimensions, tolerances, datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate
burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15mm (0.006in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions.
Inter-lead Flash and protrusions shall not exceed 0.25mm
(0.010in) per side.
4. Dimension b does not include Dambar protrusion.
Allowable Dambar protrusion shall be 0.08mm total in excess
of the b dimension at maximum material condition. Dambar
cannot be located on the lower radius of the foot. Minimum
space between protrusion and adjacent lead is 0.07mm.
5. Dimension D and E1 to be determined at Datum Plane H.
Package Drawing Contact:
packagedrawings@atmel.com
8X
E
2/27/14
8X, 8-lead 4.4mm Body, Plastic Thin
Shrink Small Outline Package (TSSOP)
TNR
C
A1
AT93C86A [DATASHEET]
Atmel-3408K-SEEPROM-AT93C86A-Datasheet_122015
16
10.3 8MA2 8-pad UDFN
DRAWING NO.
REV.
TITLE
GPC
8MA2
H
11/2/15
8MA2, 8-pad 2 x 3 x 0.6mm Body, Thermally
Enhanced Plastic Ultra Thin Dual Flat No-Lead
Package (UDFN)
YNZ
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
NOTE
A
0.50
0.55
0.60
A1
0.0
0.02
0.05
A2
-
-
0.55
D
1.90
2.00
2.10
D2
1.40
1.50
1.60
E
2.90
3.00
3.10
E2
1.20
1.30
1.40
b 0.18
0.25
0.30
3
C
0.152 REF
L
0.35
0.40
0.45
e
0.50 BSC
K
0.20
-
-
TOP VIEW
SIDE VIEW
BOTTOM VIEW
Package Drawing Contact:
packagedrawings@atmel.com
C
E
Pin 1 ID
D
8
7
6
5
1
2
3
4
A
A1
A2
D2
E2
e (6x)
L (8x)
b (8x)
Pin#1 ID
K
1
2
3
4
8
7
6
5
Notes:
1. This drawing is for general information only. Refer to
Drawing MO-229, for proper dimensions, tolerances,
datums, etc.
2. The Pin #1 ID is a laser-marked feature on Top View.
3. Dimensions b applies to metallized terminal and is
measured between 0.15 mm and 0.30 mm from the
terminal tip. If the terminal has the optional radius on
the other end of the terminal, the dimension should
not be measured in that radius area.
4. The Pin #1 ID on the Bottom View is an orientation
feature on the thermal pad.
C
17
AT93C86A [DATASHEET]
Atmel-3408K-SEEPROM-AT93C86A-Datasheet_122015
10.4 8P3 8-lead PDIP
DRAWING NO.
REV.
TITLE
GPC
Notes:
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
NOTE
D
D1
E
E1
e
L
b2
b
A2 A
1
N
eA
c
b3
4 PLCS
A
-
-
5.334
2
A1
0.381
-
-
A2 2.921
3.302
4.953
b
0.356 0.457 0.559 5
b2
1.143 1.524 1.778 6
b3
0.762 0.991 1.143 6
c
0.203 0.254 0.356
D
9.017 9.271 10.160
3
D1
0.127 0.000 0.000 3
E
7.620 7.874 8.255 4
E1 6.096
6.350
7.112
3
e 2.540
BSC
eA 7.620
BSC
4
L 2.921 3.302 3.810
2
Top View
Side View
End View
Package Drawing Contact:
packagedrawings@atmel.com
A1
Gage Plane
.381
8P3
E
07/31/14
8P3, 8-lead, 0.300 Wide Body, Plastic Dual
In-line Package (PDIP)
PTC
v
0.254
m C
AT93C86A [DATASHEET]
Atmel-3408K-SEEPROM-AT93C86A-Datasheet_122015
18
11.
Revision History
Revision No.
Date
Comments
3408K
12/2015
Correct Ordering Code Detail and update the 8S1 and 8MA2 package drawings.
3408J
01/2015
Add the UDFN extended quantity option and update the ordering information section.
Update the 8MA2 and 8P3 package drawings.
3408I
08/2014
Update pinouts, 8MA2 package drawing, grammatical changes, document template,
logos, and disclaimer page. No changes to functional specification.
3408H
01/2007
Add Bottom View to page 1 Ultra Thin MiniMap package drawing page 4 revise Note 1
added ensured by characterization.
3408G
07/2006
Revision history implemented.
Delete Preliminary status from datasheet; Add Ultra Thin description to MLP 2x3
package; Delete 1.8V not available on Figure 1 Note; Add 1.8V range on Table 4 under
Write Cycle Time.
Atmel Corporation
1600 Technology Drive, San Jose, CA 95110 USA
T: (+1)(408) 441.0311
F: (+1)(408) 436.4200
2015 Atmel Corporation. / Rev.: Atmel-3408K-SEEPROM-AT93C86A-Datasheet_122015.
Atmel
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