| Secciones |
|---|
| Foros Electrónica |
|
|
| Boletines de correo |
 |
+
-
+
-
IN+
IN-
OUT
IN+
IN-
OUT
TL072 (each amplifier)
TL074 (each amplifier)
TL071
OFFSET N1
OFFSET N2
,
, , ,
SLOS080M - SEPTEMBER 1978 - REVISED JUNE 2015
TL07xx Low-Noise JFET-Input Operational Amplifiers
1 Features
3 Description
The TL07xx JFET-input operational amplifier family is
1
•
Low Power Consumption
designed
to
offer
a
wider
selection
than
any
•
Wide Common-Mode and Differential Voltage
previously developed operational amplifier family.
Ranges
Each of these JFET-input operational amplifiers
•
Low Input Bias and Offset Currents
incorporates well-matched, high-voltage JFET and
bipolar transistors in a monolithic integrated circuit.
•
Output Short-Circuit Protection
•
Low Total Harmonic Distortion: 0.003% Typical
The devices feature high slew rates, low-input bias
and
offset
currents,
and
low
offset-voltage
•
Low Noise
temperature coefficient. The low harmonic distortion
V
n
= 18 nV/
√Hz Typ at f = 1 kHz
and low noise make the TL07xseries ideally suited for
•
High-Input Impedance: JFET Input Stage
high-fidelity and audio pre-amplifier applications.
•
Internal Frequency Compensation
Offset adjustment and external compensation options
are available within the TL07x family.
•
Latch-Up-Free Operation
•
High Slew Rate: 13 V/
μs Typical
Device
•
Common-Mode Input Voltage Range
PART NUMBER
PACKAGE
BODY SIZE (NOM)
Includes V
CC+
SOIC (14)
8.65 mm × 3.91 mm
TL07xxD
SOIC (8)
4.90 mm x 3.90 mm
2 Applications
TL07xxFK
LCCC (20)
8.89 mm × 8.89 mm
•
Motor Integrated Systems: UPS
TL07xxJG
PDIP (8)
9.59 mm x 6.67 mm
•
Drives and Control Solutions: AC Inverter and VF
TL074xJ
CDIP (14)
19.56 mm × 6.92 mm
Drives
TL07xxP
PDIP (8)
9.59 mm x 6.35 mm
•
Renewables: Solar Inverters
TL07xxPS
SO (8)
6.20 mm x 5.30 mm
•
Pro Audio Mixers
TL074xN
PDIP (14)
19.3 mm × 6.35 mm
•
DLP Front Projection System
TL074xNS
SO (14)
10.30 mm × 5.30 mm
•
Oscilloscopes
TL07xxPW
TSSOP (8)
4.40 mm x 3.00 mm
TL074xPW
TSSOP (14)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Symbols
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
, , , ,
SLOS080M - SEPTEMBER 1978 - REVISED JUNE 2015
Table of Contents
8.3
Feature Description.................................................
1
Features ..................................................................
8.4
Device Functional Modes........................................
2
Applications ...........................................................
9
Application and Implementation ........................
3
Description .............................................................
9.1
Application Information............................................
4
Revision History.....................................................
9.2
Typical Application .................................................
5
Pin Configuration and Functions .........................
9.3
System Examples ...................................................
6
Specifications.........................................................
10
Power Supply Recommendations .....................
6.1
Absolute Maximum Ratings ......................................
11
Layout...................................................................
6.2
ESD Ratings..............................................................
11.1
Layout Guidelines .................................................
6.3
Recommended Operating Conditions .......................
11.2
Layout Example ....................................................
6.4
Thermal Information .................................................
12
Device and Documentation Support .................
6.5
Electrical Characteristics, TL07xC, TL07xAC,
TL07xBC, TL07xI ......................................................
12.1
Documentation Support ........................................
6.6
Electrical Characteristics, TL07xM............................
12.2
Related Links ........................................................
6.7
Switching Characteristics ..........................................
12.3
Community Resources..........................................
6.8
Typical Characteristics ..............................................
12.4
Trademarks ...........................................................
12.5
Electrostatic Discharge Caution ............................
7
Parameter Measurement Information ................
12.6
Glossary ................................................................
8
Detailed Description ............................................
13
Mechanical, Packaging, and Orderable
8.1
Overview .................................................................
Information ...........................................................
8.2
Functional Block Diagram .......................................
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision L (February 2014) to Revision M
Page
•
Added Device Information table, Pin Configuration and Functions section, ESD Ratings table, Feature Description
section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations
section, Layout section ...........................................................................................................................................................
•
Moved Typical Characteristics into Specifications section. ...................................................................................................
Changes from Revision K (January 2014) to Revision L
Page
•
Moved T
stg
to Handling Ratings table ....................................................................................................................................
•
Added missing Electric Characteristics table ........................................................................................................................
•
Added Device and Documentation Support section.............................................................................................................
•
Added Mechanical, Packaging, and Orderable Information section.....................................................................................
Changes from Revision J (March 2005) to Revision K
Page
•
Updated document to new TI datasheet format - no specification changes. .........................................................................
•
Added ESD warning .............................................................................................................................................................
2
Copyright © 1978-2015, Texas Instruments Incorporated
Product Folder Links:
1IN+
NC
V
CC+
NC
2IN+
3
2
1
20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
4IN+
NC
V
CC-
NC
3IN+
1IN
-
1OUT
NC
3IN
-
4IN
-
2IN
-
NC
3OUT
4OUT
2OUT
NC
V
CC+
NC
OUT
NC
3
2
1
20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
NC
IN-
NC
IN+
NC
NC
OFFSET
N1
NC
NC
NC
NC
NC
OFFSET
N2
NC
CC
-
V
NC
2OUT
NC
2IN-
NC
3
2
1
20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
NC
1IN-
NC
1IN+
NC
NC
1OUT
NC
NC
NC
NC
NC
2IN+
CC
-
V
CC+
V
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OUT
1IN-
1IN+
V
CC+
2IN+
2IN-
2OUT
4OUT
4IN-
4IN+
V
CC-
3IN+
3IN-
3OUT
1
2
3
4
5
10
9
8
7
6
NC
1OUT
1IN-
1IN+
V
CC-
NC
V
CC+
2OUT
2IN-
2IN+
1
2
3
4
8
7
6
5
1OUT
1IN-
1IN+
V
CC-
V
CC+
2OUT
2IN-
2IN+
1
2
3
4
8
7
6
5
OFFSET N1
IN-
IN+
V
CC-
NC
V
CC+
OUT
OFFSET N2
,
, , ,
SLOS080M - SEPTEMBER 1978 - REVISED JUNE 2015
5 Pin Configuration and Functions
TL071x D, P, and PS Package
TL072x D, JG, P, PS and PW Package
8-Pin SOIC, PDIP, SO
8-Pin SOIC, CDIP, PDIP, SO
Top View
Top View
TL074x D, J, N , NS, PW, and W Package
TL072 U Package
14-Pin SOIC, CDIP, PDIP, SO and CFP
10-Pin CFP
Top View
Top View
TL071 FK Package
TL072 FK Package
20-Pin LCCC
20-Pin LCCC
Top View
Top View
TL074 FK Package
20-Pin LCCC
Top View
Copyright © 1978-2015, Texas Instruments Incorporated
3
Product Folder Links:
, , , ,
SLOS080M - SEPTEMBER 1978 - REVISED JUNE 2015
Pin Functions
PIN
TL071
TL072
TL074
SOIC,
I/O
DESCRIPTION
SOIC,
SOIC,
NAME
CDIP,
PDIP,
LCCC
CDIP,
CFP
LCCC
LCCC
PDIP,
SO
PDIP, SO
SO, CFP
1IN-
—
—
2
3
5
2
3
I
Inverting input
1IN+
—
—
3
4
7
3
4
I
Non-Inverting input
1OUT
—
—
1
2
2
1
2
O
Output
2IN-
—
—
6
7
15
6
9
I
Inverting input
2IN+
—
—
5
6
12
5
8
I
Non-Inverting input
2OUT
—
—
7
8
17
7
10
O
Output
3IN-
—
—
—
—
—
9
13
I
Inverting input
3IN+
—
—
—
—
—
10
14
I
Non-Inverting input
3OUT
—
—
—
—
—
8
12
O
Output
4IN-
—
—
—
—
—
13
19
I
Inverting input
4IN+
—
—
—
—
—
12
18
I
Non-Inverting input
4OUT
—
—
—
—
—
14
20
O
Output
IN-
2
5
—
—
—
—
—
I
Inverting input
IN+
3
7
—
—
—
—
—
I
Non-Inverting input
1
1
3
—
4
—
1
1
6
—
8
—
9
9
NC
(1)
8
11
—
11
—
5
—
Do not connect
13
13
7
14
14
11
16
0
16
15
18
18
19
17
19
20
OFFSET N1
1
2
—
—
—
—
—
—
Input offset adjustment
OFFSET N2
5
12
—
—
—
—
—
—
Input offset adjustment
OUT
6
15
—
—
—
—
—
O
Output
V
CC-
4
10
4
5
10
11
16
—
Power supply
V
CC+
7
17
8
9
20
4
6
—
Power supply
(1)
NC - No internal connection
4
Copyright © 1978-2015, Texas Instruments Incorporated
Product Folder Links:
,
, , ,
SLOS080M - SEPTEMBER 1978 - REVISED JUNE 2015
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
V
CC+
- V
CC-
Supply voltage
(2)
-18
18
V
V
ID
Differential input voltage
(3)
-30
30
V
V
I
Input voltage
(2) (4)
-15
15
V
Duration of output short circuit
(5)
Unlimited
T
J
Operating Virtual Junction Temperature
150
°C
Case temperature for 60 seconds - FK package
260
°C
Lead temperature 1.8 mm (1/16 inch) from case for 10 seconds
300
°C
T
stg
Storage temperature
-65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
All voltage values, except differential voltages, are with respect to the midpoint between V
CC+
and V
CC
-
.
(3)
Differential voltages are at IN+, with respect to IN
-.
(4)
The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less.
(5)
The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be limited to ensure that the
dissipation rating is not exceeded.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±2000
V
(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
±1000
C101
(2)
(1)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2)
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
V
CC+
Supply voltage
5
15
V
V
CC-
Supply voltage
-5
-15
V
V
CM
Common-mode voltage
V
CC-
+ 4
V
CC+
- 4
V
TL07xM
-55
125
TL08xQ
-40
125
T
A
Operating free-air temperature
°C
TL07xI
-40
85
TL07xA, TL07xB, TL07xC
0
70
6.4 Thermal Information
TL071/TL072/TL074
FK
PW
D (SOIC)
J (CDIP)
N (PDIP)
NS (SO)
THERMAL METRIC
(1)
(LCCC)
(TSSOP)
UNIT
8
14
20
8
14
8
14
14
8
14
8 PINS
PINS
PINS
PINS
PINS
PINS
PINS
PINS
PINS
PINS PINS
Junction-to-ambient
R
ΘJA
97
86
—
—
—
85
80
95
76
150
113
°C/W
thermal resistance
Junction-to-case (top)
R
ΘJC(top)
—
—
5.61
15.05
14.5
—
—
—
—
—
—
°C/W
thermal resistance
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report,
Copyright © 1978-2015, Texas Instruments Incorporated
5
Product Folder Links:
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SLOS080M - SEPTEMBER 1978 - REVISED JUNE 2015
6.5 Electrical Characteristics, TL07xC, TL07xAC, TL07xBC, TL07xI
V
CC
± = ±15 V (unless otherwise noted)
TL071C, TL072C,
TL071AC, TL072AC,
TL071BC, TL072BC,
TL071I, TL072I, TL074I
TEST
TL074C
TL074AC
TL074BC
PARAMETER
T
A
(2)
UNIT
CONDITIONS
(1)
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
25 °C
3
10
3
6
2
3
3
6
Input offset
V
IO
V
O
= 0,
R
S
= 50
Ω
mV
voltage
Full range
13
7.5
5
8
Temperature
coefficient of
V
O
= 0,
R
S
= 50
Ω
Full range
18
18
18
18
µV/ °C
α
V
IO
input offset
voltage
25 °C
5
100
5
100
5
100
5
100
pA
Input offset
I
IO
V
O
= 0
current
Full range
10
2
2
2
nA
25 °C
65
200
65
200
65
200
65
200
pA
Input bias
I
IB
V
O
= 0
current
(3)
Full range
7
7
7
7
nA
Common-mode
-12
-12
-12
-12
V
ICR
input voltage
25 °C
±11
to
±11
to
±11
to
±11
to
V
range
15
15
15
15
R
L
= 10 k
Ω
25 °C
±12
±13.5
±12
±13.5
±12
±13.5
±12
±13.5
Maximum peak
V
OM
output voltage
R
L
≥ 10 kΩ
±12
±12
±12
±12
V
Full range
swing
R
L
≥ 2 kΩ
±10
±10
±10
±10
Large-signal
25 °C
25
200
50
200
50
200
50
200
differential
A
VD
V
O
= ±10 V,
R
L
≥ 2 kΩ
V/mV
voltage
Full range
15
25
25
25
amplification
Utility-gain
B
1
25 °C
3
3
3
3
MHz
bandwidth
r
I
Input resistance
25 °C
Ω
10
12
10
12
10
12
10
12
V
IC
= V
ICR
min,
Common-mode
CMRR
25 °C
70
100
75
100
75
100
75
100
dB
rejection ratio
V
O
= 0,
R
S
= 50
Ω
Supply-voltage
V
CC
= ±9 V to ±15 V,
k
SVR
rejection ratio
25 °C
70
100
80
100
80
100
80
100
dB
V
O
= 0,
R
S
= 50
Ω
(
ΔV
CC ±
/
ΔV
IO
)
Supply current
I
CC
V
O
= 0,
No load
25 °C
1.4
2.5
1.4
2.5
1.4
2.5
1.4
2.5
mA
(each amplifier)
Crosstalk
V
O1
/V
O2
A
VD
= 100
25 °C
120
120
120
120
dB
attenuation
(1)
All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified.
(2)
Full range is T
A
= 0 °C to 70 °C for TL07_C,TL07_AC, TL07_BC and is T
A
= -40 °C to 85 °C for TL07_I.
(3)
Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in
. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as
possible.
6
Copyright © 1978-2015, Texas Instruments Incorporated
Product Folder Links:
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, , ,
SLOS080M - SEPTEMBER 1978 - REVISED JUNE 2015
6.6 Electrical Characteristics, TL07xM
V
CC ±
= ±15 V (unless otherwise noted)
TL071M, TL072M
TL074M
PARAMETER
TEST CONDITIONS
(1)
T
A
(2)
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
25 °C
3
6
3
9
V
IO
Input offset voltage
V
O
= 0, R
S
= 50
Ω¦
mV
Full range
9
15
Temperature coefficient
α
VIO
V
O
= 0, R
S
= 50
Ω¦
Full range
18
18
μV/ °C
of input offset voltage
25 °C
5
100
5
100
pA
I
IO
Input offset current
V
O
= 0
Full range
20
20
nA
25 °C
65
200
65
200
pA
I
IB
Input bias current
V
O
= 0
50
20
nA
Common-mode input
V
ICR
25 °C
±11
-12 to 15
±11 -12 to 15
V
voltage range
R
L
= 10 k
Ω¦
25 °C
±12
±13.5
±12
±13.5
Maximum peak output
V
OM
R
L
≥ 10 kΩ¦
±12
±12
V
voltage swing
Full range
R
L
≥ 2 kΩ¦
±10
±10
25 °C
35
200
35
200
Large-signal differential
A
VD
V
O
= ±10 V, R
L
≥ 2 kΩ¦
V/mV
voltage amplification
15
15
B
1
Unity-gain bandwidth
3
3
MHz
r
i
Input resistance
Ω¦
10
12
10
12
Common-mode
V
IC
= V
ICR
min,
CMRR
25 °C
80
86
80
86
dB
rejection ratio
V
O
= 0, R
S
= 50
Ω¦
Supply-voltage rejection
V
CC
= ±9 V to ±15 V,
k
SVR
25 °C
80
86
80
86
dB
ratio (
ΔV
CC ±
/
ΔV
IO
)
V
O
= 0, R
S
= 50
Ω¦
Supply current
I
CC
V
O
= 0, No load
25 °C
1.4
2.5
1.4
2.5
mA
(each amplifier)
V
O1
/V
O2
Crosstalk attenuation
A
VD
= 100
25 °C
120
120
dB
(1)
Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in
. Pulse techniques must be used that will maintain the junction temperature as close to the ambient temperature as
possible.
(2)
All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. Full range is
T
A
= -55 °C to 125 °C.
6.7 Switching Characteristics
V
CC ±
= ±15 V, T
A
= 25 °C
TL07xC, TL07xAC,
TL07xM
TL07xBC, TL07xI
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
Slew rate at unity
V
I
= 10 V,
R
L
= 2 k
Ω¦,
SR
5
13
8
13
V/
μs
gain
C
L
= 100 pF,
See
0.1
0.1
μs
Rise-time overshoot
V
I
= 20 V,
R
L
= 2 k
Ω¦,
t
r
factor
C
L
= 100 pF,
See
20%
20%
f = 1 kHz
18
18
nV/
√Hz
Equivalent input noise
V
n
R
S
= 20
Ω¦
voltage
f = 10 Hz to 10 kHz
4
4
μV
Equivalent input noise
I
n
R
S
= 20
Ω¦,
f = 1 kHz
0.01
0.01
pA/
√Hz
current
V
I
rms = 6 V,
Total harmonic
A
VD
= 1,
THD
R
L
≥ 2 kΩ¦,
0.003%
0.003%
distortion
RS
≤ 1 kΩ¦,
f = 1 kHz,
Copyright © 1978-2015, Texas Instruments Incorporated
7
Product Folder Links:
II
B
-
In
p
u
t B
ia
s C
u
rr
e
n
t
-
n
A
T
A
- Free-Air Temperature - °C
IBI
10
1
0.1
0.01
100
-75
-50
-25
0
25
50
75
100
125
V
CC
±
= ±15 V
R
L
= 10 kΩ
T
A
= 25 °C
See Figure 2
±15
±12.5
±10
±7.5
±5
±2.5
0
V
O
M
-
M
a
x
im
u
m P
e
a
k O
u
tp
u
t V
o
lt
a
g
e
-
V
f - Frequency - Hz
100
1 k
10 k
100 k
1 M
10 M
V
OM
V
CC
±
= ±5 V
V
CC
±
= ±10 V
V
CC
±
= ±15 V
, , , ,
SLOS080M - SEPTEMBER 1978 - REVISED JUNE 2015
6.8 Typical Characteristics
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various
devices.
Table 1. Table of Graphs
Figure
I
IB
Input bias current
versus Free-air temperature
versus Frequency
,
,
versus Free-air temperature
V
OM
Maximum peak output voltage
versus Load resistance
versus Supply voltage
Large signal differential voltage
versus Free-air temperature
A
VD
amplification
versus Load resistance
Phase shift
versus Frequency
Normalized unity-gain bandwidth
versus Free-air temperature
Normalized phase shift
versus Free-air temperature
CMRR
Common-mode rejection ratio
versus Free-air temperature
versus Free-air temperature
I
CC
Supply current
versus Supply voltage
P
D
Total power dissipation
versus Free-air temperature
Normalized slew rate
versus Free-air temperature
V
n
Equivalent input noise voltage
versus Frequency
THD
Total harmonic distortion
versus Frequency
Large-signal pulse response
versus Time
V
O
Output voltage
versus Elapsed time
Figure 2. Maximum Peak Output Voltage vs Frequency
Figure 1. Input Bias Current vs Free-Air Temperature
8
Copyright © 1978-2015, Texas Instruments Incorporated
Product Folder Links:
0
0
V
O
M
-
M
a
x
im
u
m P
e
a
k O
u
tp
u
t V
o
lt
a
g
e
-
V
|V
CC
±
| - Supply Voltage - V
16
±15
2
4
6
8
10
12
14
±2.5
±5
±7.5
±10
±12.5
R
L
= 10 kΩ
T
A
= 25 °C
V
OM
-75
1
V
o
lt
a
g
e
A
m
p
li
fi
c
a
ti
o
n
-
V
/m
V
T
A
- Free-Air Temperature - °C
125
1000
-50
-25
0
25
50
75
100
2
4
10
20
40
100
200
400
V
CC
±
= ±15 V
V
O
= ±10 V
R
L
= 2 kΩ
A
V
D
-
L
a
rg
e
-S
ig
n
a
l D
if
fe
re
n
ti
a
l
A
VD
-75
0
V
O
M
-
M
a
x
im
u
m P
e
a
k O
u
tp
u
t V
o
lt
a
g
e
-
V
T
A
- Free-Air Temperature - °C
125
±15
-50
-25
0
25
50
75
100
±2.5
±5
±7.5
±10
±12.5
R
L
= 10 k
Ω
V
CC ±
= ±15 V
See Figure 2
V
OM
R
L
= 2 kΩ
8
0.1
0
R
L
- Load Resistance - kΩ
10
±15
±2.5
±5
±7.5
±10
±12.5
V
CC ±
= ±15 V
T
A
= 25 °C
See Figure 2
0.2
0.4
0.7 1
2
4
7
V
O
M
-
M
a
x
im
u
m P
e
a
k O
u
tp
u
t V
o
lt
a
g
e
-
V
V
OM
8
10 M
1 M
100 k
10 k
1 k
100
f - Frequency - Hz
V
O
M
-
M
a
x
im
u
m P
e
a
k O
u
tp
u
t V
o
lt
a
g
e
-
V
0
±2.5
±5
±7.5
±10
±12.5
±15
See Figure 2
T
A
= 25 °C
R
L
= 2 kΩ
V
CC ±
= ±10 V
V
CC ±
= ±5 V
V
OM
V
CC ±
= ±15 V
8
,
, , ,
SLOS080M - SEPTEMBER 1978 - REVISED JUNE 2015
Figure 4. Maximum Peak Output Voltage vs Frequency
Figure 3. Maximum Peak Output Voltage vs Frequency
Figure 5. Maximum Peak Output Voltage vs Free-Air
Figure 6. Maximum Peak Output Voltage vs Load
Temperature
Resistance
Figure 7. Maximum Peak Output Voltage vs Supply Voltage
Figure 8. Large-Signal Differential Voltage Amplification vs
Free-Air Temperature
Copyright © 1978-2015, Texas Instruments Incorporated
9
Product Folder Links:
-75
0
T
A
- Free-Air Temperature - °C
125
2
-50
-25
0
25
50
75
100
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
V
CC
±
= ±15 V
No Signal
No Load
IC
C
-
S
u
p
p
ly C
u
rr
e
n
t P
e
r
A
m
p
li
fi
e
r
-
m
A
CC
±
I
-75
0
T
A
- Free-Air Temperature -C
°
125
250
-50
-25
0
25
50
75
100
25
50
75
100
125
150
175
200
225
V
CC
±
= 15 V
±
No Signal
No Load
TL074
TL071
TL072
-
T
ota
l
P
ower
Di
ssi
pati
on
-
m
W
P
D
-75
83
C
M
R
R
-
C
o
m
m
o
n
-M
o
d
e R
e
je
c
ti
o
n R
a
ti
o
-
d
B
T
A
- Free-Air Temperature - °C
125
89
-50
-25
0
25
50
75
100
84
85
86
87
88
V
CC
±
= ±15 V
R
L
= 10 k
Ω
0
0
|V
CC ±
| - Supply Voltage - V
16
2
2
4
6
8
10
12
14
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
T
A
= 25 °C
No Signal
No Load
IC
C
-
S
u
p
p
ly C
u
rr
e
n
t P
e
r
A
m
p
li
fi
e
r
-
m
A
CC
±
I
1.02
1.01
1
0.99
0.98
1.03
0.97
-75
0.7
N
o
rm
a
li
z
e
d U
n
it
y
-G
a
in B
a
n
d
w
id
th
T
A
- Free-Air Temperature - °C
125
1.3
-50
-25
0
25
50
75
100
0.8
0.9
1
1.1
1.2
Unity-Gain Bandwidth
V
CC
±
= ±15 V
R
L
= 2 k
Ω
f = B
1
for Phase Shift
Phase Shift
N
o
rm
a
li
z
e
d P
h
a
s
e S
h
if
t
, , , ,
SLOS080M - SEPTEMBER 1978 - REVISED JUNE 2015
Figure 9. Large-Signal Differential Voltage Amplification and
Figure 10. Normalized Unity-Gain Bandwidth and Phase
Phase Shift vs Frequency
Shift vs Free-Air Temperature
Figure 11. Common-Mode Rejection Ratio vs Free-Air
Figure 12. Supply Current Per Amplifier vs Supply Voltage
Temperature
Figure 13. Supply Current Per Amplifier vs Free-Air
Figure 14. Total Power Dissipation vs Free-Air Temperature
Temperature
10
Copyright © 1978-2015, Texas Instruments Incorporated
Product Folder Links:
-6
t - Time - µs
3.5
6
0
0.5
1
1.5
2
2.5
3
-4
-2
0
2
4
Output
Input
V
CC
±
= ±15 V
R
L
= 2 kΩ
T
A
= 25 °C
C
L
= 100 pF
V
O
V
I
-
In
p
u
t a
n
d O
u
tp
u
t V
o
lt
a
g
e
s
-
V
and
0.001
T
H
D
-
T
o
ta
l H
a
rm
o
n
ic D
is
to
rt
io
n
-
%
1
40 k
10 k
4 k
1 k
400
100 k
f - Frequency - Hz
100
0.004
0.01
0.04
0.1
0.4
V
CC
±
= ±15 V
A
VD
= 1
V
I(RMS)
= 6 V
T
A
= 25 °C
10
0
-
E
q
u
iv
a
le
n
t I
n
p
u
t N
o
is
e V
o
lt
a
g
e
-
n
V
/H
z
f - Frequency - Hz
100 k
50
10
20
30
40
V
CC
±
= ±15 V
A
VD
= 10
R
S
= 20
Ω
T
A
= 25 °C
40 100
400 1 k
4 k 10 k
40 k
nV/
Hz
V
n
,
, , ,
SLOS080M - SEPTEMBER 1978 - REVISED JUNE 2015
Figure 16. Equivalent Input Noise Voltage vs Frequency
Figure 15. Normalized Slew Rate vs Free-Air Temperature
Figure 17. Total Harmonic Distortion vs Frequency
Figure 18. Voltage-Follower Large-Signal Pulse Response
Figure 19. Output Voltage vs Elapsed Time
Copyright © 1978-2015, Texas Instruments Incorporated
11
Product Folder Links:
N1
100 k
Ω¦
+
-
TL071
N2
1.5 k
Ω¦
V
CC-
OUT
IN-
IN+
VI
10 k
Ω¦
1 k
Ω¦
RL
CL = 100 pF
+
-
OUT
VI
CL = 100 pF
RL = 2 k٦
+
-
OUT
, , , ,
SLOS080M - SEPTEMBER 1978 - REVISED JUNE 2015
7 Parameter Measurement Information
Figure 20. Unity-Gain Amplifier
Figure 21. Gain-of-10 Inverting Amplifier
Figure 22. Input Offset-Voltage Null Circuit
12
Copyright © 1978-2015, Texas Instruments Incorporated
Product Folder Links:
C1
V
CC+
IN+
V
CC-
1080 Ω¦
1080 Ω¦
IN-
TL071 Only
64 Ω¦
128 Ω¦
64 Ω¦
All component values shown are nominal.
OFFSET
N1
OFFSET
N2
OUT
18 pF
COMPONENT COUNT
†
COMPONENT
TYPE
TL071
TL072
TL074
Resistors
11
22
44
Resistors
Transistors
11
14
22
28
44
56
Transistors
JFET
14
2
28
4
56
6
JFET
Diodes
2
1
4
2
6
4
Diodes
Capacitors
1
1
2
2
4
4
Capacitors
epi-FET
1
1
2
2
4
4
†
Includes bias and trim circuitry
,
, , ,
SLOS080M - SEPTEMBER 1978 - REVISED JUNE 2015
8 Detailed Description
8.1 Overview
The JFET-input operational amplifiers is in the TL07xx series are similar to the TL08x series, with low input bias
and offset currents and fast slew rate. The low harmonic distortion and low noise make the TL07xx series ideally
suited for high-fidelity and audio preamplifier applications. Each amplifier features JFET inputs (for high input
impedance) coupled with bipolar output stages integrated on a single monolithic chip.
The C-suffix devices are characterized for operation from 0 °C to 70 °C. The I-suffix devices are characterized for
operation from
-40 °C to 85 °C. The M-suffix devices are characterized for operation over the full military
temperature range of
-55 °C to 125 °C.
8.2 Functional Block Diagram
Copyright © 1978-2015, Texas Instruments Incorporated
13
Product Folder Links:
, , , ,
SLOS080M - SEPTEMBER 1978 - REVISED JUNE 2015
8.3 Feature Description
8.3.1 Total Harmonic Distortion
Harmonic distortions to an audio signal are created by electronic components in a circuit. Total harmonic
distortion (THD) is a measure of harmonic distortions accumulated by a signal in an audio system. These devices
have a very low THD of 0.003% meaning that the TL07x devices will add little harmonic distortion when used in
audio signal applications.
8.3.2 Slew Rate
The slew rate is the rate at which an operational amplifier can change its output when there is a change on the
input. These devices have a 13-V/
μs slew rate.
8.4 Device Functional Modes
These devices are powered on when the supply is connected. This device can be operated as a single-supply
operational amplifier or dual-supply amplifier depending on the application.
14
Copyright © 1978-2015, Texas Instruments Incorporated
Product Folder Links:
V
RF
A =
RI
-
V
1.8
A =
3.6
0.5
= -
-
V
VOUT
A =
VIN
Vsup+
+
V
OUT
RF
V
IN
RI
Vsup-
,
, , ,
SLOS080M - SEPTEMBER 1978 - REVISED JUNE 2015
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
A typical application for an operational amplifier is an inverting amplifier. This amplifier takes a positive voltage on
the input, and makes it a negative voltage of the same magnitude. In the same manner, it also makes negative
voltages positive.
9.2 Typical Application
Figure 23. Inverting Amplifier
9.2.1 Design Requirements
The supply voltage must be chosen such that it is larger than the input voltage range and output range. For
instance, this application will scale a signal of ±0.5 V to ±1.8 V. Setting the supply at ±12 V is sufficient to
accommodate this application.
9.2.2 Detailed Design Procedure
Determine the gain required by the inverting amplifier:
(1)
(2)
Once the desired gain is determined, choose a value for RI or RF. Choosing a value in the kilohm range is
desirable because the amplifier circuit will use currents in the milliamp range. This ensures the part will not draw
too much current. This example will choose 10 k
Ω for RI which means 36 kΩ will be used for RF. This was
determined by
(3)
Copyright © 1978-2015, Texas Instruments Incorporated
15
Product Folder Links:
+
-
-15 V
15 V
Output
1 k
Ω¦
9.1 k
Ω¦
3.3 k
Ω¦
C
F
= 3.3
µF
R
F
= 100 k
Ω¦
3.3 k
Ω¦
TL071
f =
1
2
R
F
C
F
+
-
R2
R1
C1
C2
R3
C3
V
CC-
V
CC+
TL071
Output
Input
C1 = C2 =
C3
2
= 110 pF
f
O
=
1
2Ď€ R1 C1
= 1 kHz
R1 = R2 = 2R3 = 1.5 MΩ
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
0
0.5
1
1.5
2
V
o
lt
s
Time (ms)
VIN
VOUT
, , , ,
SLOS080M - SEPTEMBER 1978 - REVISED JUNE 2015
Typical Application (continued)
9.2.3 Application Curve
Figure 24. Input and Output Voltages of the Inverting Amplifier
9.3 System Examples
Figure 25. 0.5-Hz Square-Wave Oscillator
Figure 26. High-Q Notch Filter
16
Copyright © 1978-2015, Texas Instruments Incorporated
Product Folder Links:
0.1
F
µ
0.1
µF
+
-
10 k
Ω¦
50
Ω¦
100 k
Ω¦
N1
OUT
1 M
Ω¦
V
CC+
10 k
Ω¦
10 k
Ω¦
TL071
N2
IN-
IN+
-15 V
6 sin ωt
+
-
6 cos ωt
+
-
88.4 k
Ω¦
V
CC+
V
CC-
V
CC+
V
CC-
1N4148
18 pF
18 pF
1 k
Ω¦
18 k
Ω¦ (see Note A)
15 V
TL072
TL072
88.4 k
Ω¦
88.4 k
Ω¦
18 pF
1 k
Ω¦
18 k
Ω¦ (see Note A)
1N4148
,
, , ,
SLOS080M - SEPTEMBER 1978 - REVISED JUNE 2015
System Examples (continued)
Figure 27. 100-kHz Quadrature Oscillator
Figure 28. AC Amplifier
10 Power Supply Recommendations
CAUTION
Supply voltages larger than 36 V for a single-supply or outside the range of ±18 V for a
dual-supply can permanently damage the device (see the
Place 0.1-
μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, refer to the
.
11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance
power sources local to the analog circuitry.
-
Connect low-ESR, 0.1-
μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single
supply applications.
•
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current. For more detailed information, refer to
Circuit Board Layout Techniques,
•
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as
opposed to in parallel with the noisy trace.
•
Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance, as shown in
•
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
•
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
Copyright © 1978-2015, Texas Instruments Incorporated
17
Product Folder Links:
+
RIN
RG
RF
VOUT
VIN
NC
VCC+
IN1
Ă
IN1+
VCC
Ă
NC
OUT
NC
RG
RIN
RF
GND
VIN
VS-
GND
VS+
GND
Run the input traces as far
away from the supply lines
as possible
Only needed for
dual-supply
operation
Place components close to
device and to each other to
reduce parasitic errors
Use low-ESR, ceramic
bypass capacitor
(or GND for single supply)
Ground (GND) plane on another layer
VOUT
, , , ,
SLOS080M - SEPTEMBER 1978 - REVISED JUNE 2015
Layout Guidelines (continued)
leakage currents from nearby traces that are at different potentials.
11.2 Layout Example
Figure 29. Operational Amplifier Board Layout for Noninverting Configuration
Figure 30. Operational Amplifier Schematic for Noninverting Configuration
18
Copyright © 1978-2015, Texas Instruments Incorporated
Product Folder Links:
,
, , ,
SLOS080M - SEPTEMBER 1978 - REVISED JUNE 2015
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
Circuit Board Layout Techniques,
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
TECHNICAL
TOOLS &
SUPPORT &
PARTS
PRODUCT FOLDER
SAMPLE & BUY
DOCUMENTS
SOFTWARE
COMMUNITY
TL071
TL071A
TL071B
TL072
TL072A
TL072B
TL074
TL074A
TL074B
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's
TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
— TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
Copyright © 1978-2015, Texas Instruments Incorporated
19
Product Folder Links:
PACKAGE OPTION ADDENDUM
www.ti.com
17-Dec-2015
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp ( °C)
Device Marking
(4/5)
Samples
8102304HA
OBSOLETE
10
TBD
Call TI
Call TI
-55 to 125
81023052A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
81023052A
TL072MFKB
8102305HA
ACTIVE
CFP
U
10
1
TBD
A42
N / A for Pkg Type
-55 to 125
8102305HA
TL072M
8102305PA
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
8102305PA
TL072M
81023062A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
81023062A
TL074MFKB
8102306CA
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
8102306CA
TL074MJB
8102306DA
ACTIVE
CFP
W
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
8102306DA
TL074MWB
JM38510/11905BPA
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510
/11905BPA
JM38510/11906BCA
ACTIVE
CDIP
J
14
25
TBD
Call TI
Call TI
-55 to 125
JL147BCA
JM38510/11906BCA Q
M38510/11905BPA
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510
/11905BPA
TL071-W
ACTIVE
WAFERSALE
YS
0
TBD
Call TI
Call TI
TL071ACD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
071AC
TL071ACDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
071AC
TL071ACDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
071AC
TL071ACP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TL071ACP
TL071ACPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TL071ACP
TL071BCD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
071BC
PACKAGE OPTION ADDENDUM
www.ti.com
17-Dec-2015
Addendum-Page 2
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp ( °C)
Device Marking
(4/5)
Samples
TL071BCDE4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
071BC
TL071BCDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
071BC
TL071BCDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
071BC
TL071BCP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TL071BCP
TL071BCPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TL071BCP
TL071CD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TL071C
TL071CDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TL071C
TL071CDRE4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TL071C
TL071CDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TL071C
TL071CP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TL071CP
TL071CPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TL071CP
TL071CPSR
ACTIVE
SO
PS
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
T071
TL071CPSRG4
ACTIVE
SO
PS
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
T071
TL071CPWLE
OBSOLETE
TSSOP
PW
8
TBD
Call TI
Call TI
0 to 70
TL071ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL071I
TL071IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL071I
TL071IDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL071I
TL071IJG
OBSOLETE
CDIP
JG
8
TBD
Call TI
Call TI
-40 to 85
TL071IP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
TL071IP
PACKAGE OPTION ADDENDUM
www.ti.com
17-Dec-2015
Addendum-Page 3
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp ( °C)
Device Marking
(4/5)
Samples
TL071IPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
TL071IP
TL071MFKB
OBSOLETE
LCCC
FK
20
TBD
Call TI
Call TI
-55 to 125
TL071MJG
OBSOLETE
CDIP
JG
8
TBD
Call TI
Call TI
-55 to 125
TL071MJGB
OBSOLETE
CDIP
JG
8
TBD
Call TI
Call TI
-55 to 125
TL072ACD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
072AC
TL072ACDE4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
072AC
TL072ACDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
072AC
TL072ACDRE4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
072AC
TL072ACDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
072AC
TL072ACJG
OBSOLETE
CDIP
JG
8
TBD
Call TI
Call TI
0 to 70
TL072ACP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TL072ACP
TL072ACPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TL072ACP
TL072ACPSR
OBSOLETE
SO
PS
8
TBD
Call TI
Call TI
0 to 70
TL072ACPSRE4
OBSOLETE
SO
PS
8
TBD
Call TI
Call TI
0 to 70
TL072ACPSRG4
OBSOLETE
SO
PS
8
TBD
Call TI
Call TI
0 to 70
TL072BCD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
072BC
TL072BCDE4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
072BC
TL072BCDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
072BC
TL072BCDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
072BC
TL072BCDRE4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
072BC
TL072BCDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
072BC
PACKAGE OPTION ADDENDUM
www.ti.com
17-Dec-2015
Addendum-Page 4
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp ( °C)
Device Marking
(4/5)
Samples
TL072BCP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TL072BCP
TL072BCPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TL072BCP
TL072CD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TL072C
TL072CDE4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TL072C
TL072CDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TL072C
TL072CDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TL072C
TL072CDRE4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TL072C
TL072CDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TL072C
TL072CP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TL072CP
TL072CPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TL072CP
TL072CPSLE
OBSOLETE
SO
PS
8
TBD
Call TI
Call TI
0 to 70
TL072CPSR
ACTIVE
SO
PS
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
T072
TL072CPSRE4
ACTIVE
SO
PS
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
T072
TL072CPSRG4
ACTIVE
SO
PS
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
T072
TL072CPWR
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
T072
TL072CPWRE4
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
T072
TL072CPWRG4
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
T072
TL072ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL072I
PACKAGE OPTION ADDENDUM
www.ti.com
17-Dec-2015
Addendum-Page 5
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp ( °C)
Device Marking
(4/5)
Samples
TL072IDE4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL072I
TL072IDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL072I
TL072IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL072I
TL072IDRE4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL072I
TL072IDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL072I
TL072IP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
TL072IP
TL072IPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
TL072IP
TL072MFKB
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
81023052A
TL072MFKB
TL072MJG
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
TL072MJG
TL072MJGB
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
8102305PA
TL072M
TL072MUB
ACTIVE
CFP
U
10
1
TBD
A42
N / A for Pkg Type
-55 to 125
8102305HA
TL072M
TL074ACD
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TL074AC
TL074ACDE4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TL074AC
TL074ACDG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TL074AC
TL074ACDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TL074AC
TL074ACDRE4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TL074AC
TL074ACDRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TL074AC
TL074ACJ
OBSOLETE
CDIP
J
14
TBD
Call TI
Call TI
0 to 70
PACKAGE OPTION ADDENDUM
www.ti.com
17-Dec-2015
Addendum-Page 6
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp ( °C)
Device Marking
(4/5)
Samples
TL074ACN
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TL074ACN
TL074ACNE4
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TL074ACN
TL074ACNSR
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TL074A
TL074BCD
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TL074BC
TL074BCDE4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TL074BC
TL074BCDG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TL074BC
TL074BCDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TL074BC
TL074BCDRE4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TL074BC
TL074BCDRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TL074BC
TL074BCN
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TL074BCN
TL074BCNE4
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TL074BCN
TL074CD
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TL074C
TL074CDE4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TL074C
TL074CDG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TL074C
TL074CDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
0 to 70
TL074C
TL074CDRE4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TL074C
TL074CDRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TL074C
TL074CN
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TL074CN
PACKAGE OPTION ADDENDUM
www.ti.com
17-Dec-2015
Addendum-Page 7
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp ( °C)
Device Marking
(4/5)
Samples
TL074CNE4
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TL074CN
TL074CNSR
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TL074
TL074CNSRG4
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TL074
TL074CPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
T074
TL074CPWG4
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
T074
TL074CPWLE
OBSOLETE
TSSOP
PW
14
TBD
Call TI
Call TI
0 to 70
TL074CPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
T074
TL074CPWRE4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
T074
TL074CPWRG4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
T074
TL074ID
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL074I
TL074IDE4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL074I
TL074IDG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL074I
TL074IDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL074I
TL074IDRE4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL074I
TL074IDRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL074I
TL074IJ
OBSOLETE
CDIP
J
14
TBD
Call TI
Call TI
-40 to 85
TL074IN
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
TL074IN
TL074INE4
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
TL074IN
TL074MFK
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
TL074MFK
PACKAGE OPTION ADDENDUM
www.ti.com
17-Dec-2015
Addendum-Page 8
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp ( °C)
Device Marking
(4/5)
Samples
TL074MFKB
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
81023062A
TL074MFKB
TL074MJ
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
TL074MJ
TL074MJB
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
8102306CA
TL074MJB
TL074MWB
ACTIVE
CFP
W
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
8102306DA
TL074MWB
TL081-W
ACTIVE
WAFERSALE
YS
0
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
PACKAGE OPTION ADDENDUM
www.ti.com
17-Dec-2015
Addendum-Page 9
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TL072, TL072M, TL074, TL074M :
•
Catalog:
•
Enhanced Product:
,
•
Military:
,
NOTE: Qualified Version Definitions:
•
Catalog - TI's standard catalog product
•
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package
Type
Package
Drawing
Pins
SPQ
Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
TL071ACDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TL071BCDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TL071CDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TL071CDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TL071CPSR
SO
PS
8
2000
330.0
16.4
8.2
6.6
2.5
12.0
16.0
Q1
TL071IDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TL072ACDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TL072BCDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TL072CDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TL072CDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TL072CPSR
SO
PS
8
2000
330.0
16.4
8.2
6.6
2.5
12.0
16.0
Q1
TL072CPWR
TSSOP
PW
8
2000
330.0
12.4
7.0
3.6
1.6
8.0
12.0
Q1
TL072IDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TL072IDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TL074ACDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
TL074ACNSR
SO
NS
14
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
TL074BCDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
TL074CDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Mar-2016
Pack Materials-Page 1
Device
Package
Type
Package
Drawing
Pins
SPQ
Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
TL074CDRG4
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
TL074CPWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
TL074IDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TL071ACDR
SOIC
D
8
2500
340.5
338.1
20.6
TL071BCDR
SOIC
D
8
2500
340.5
338.1
20.6
TL071CDR
SOIC
D
8
2500
367.0
367.0
35.0
TL071CDR
SOIC
D
8
2500
340.5
338.1
20.6
TL071CPSR
SO
PS
8
2000
367.0
367.0
38.0
TL071IDR
SOIC
D
8
2500
340.5
338.1
20.6
TL072ACDR
SOIC
D
8
2500
340.5
338.1
20.6
TL072BCDR
SOIC
D
8
2500
340.5
338.1
20.6
TL072CDR
SOIC
D
8
2500
367.0
367.0
35.0
TL072CDR
SOIC
D
8
2500
340.5
338.1
20.6
TL072CPSR
SO
PS
8
2000
367.0
367.0
38.0
TL072CPWR
TSSOP
PW
8
2000
367.0
367.0
35.0
TL072IDR
SOIC
D
8
2500
340.5
338.1
20.6
TL072IDR
SOIC
D
8
2500
367.0
367.0
35.0
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Mar-2016
Pack Materials-Page 2
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TL074ACDR
SOIC
D
14
2500
333.2
345.9
28.6
TL074ACNSR
SO
NS
14
2000
367.0
367.0
38.0
TL074BCDR
SOIC
D
14
2500
333.2
345.9
28.6
TL074CDR
SOIC
D
14
2500
333.2
345.9
28.6
TL074CDRG4
SOIC
D
14
2500
333.2
345.9
28.6
TL074CPWR
TSSOP
PW
14
2000
367.0
367.0
35.0
TL074IDR
SOIC
D
14
2500
333.2
345.9
28.6
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Mar-2016
Pack Materials-Page 3
MECHANICAL DATA
MCER001A - JANUARY 1995 - REVISED JANUARY 1997
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.310 (7,87)
0.290 (7,37)
0.014 (0,36)
0.008 (0,20)
Seating Plane
4040107/C 08/96
5
4
0.065 (1,65)
0.045 (1,14)
8
1
0.020 (0,51) MIN
0.400 (10,16)
0.355 (9,00)
0.015 (0,38)
0.023 (0,58)
0.063 (1,60)
0.015 (0,38)
0.200 (5,08) MAX
0.130 (3,30) MIN
0.245 (6,22)
0.280 (7,11)
0.100 (2,54)
0
°
-15
°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
www.ti.com
PACKAGE OUTLINE
C
TYP
6.6
6.2
1.2 MAX
6X 0.65
8X 0.30
0.19
2X
1.95
0.15
0.05
(0.15) TYP
0 - 8
0.25
GAGE PLANE
0.75
0.50
A
NOTE 3
3.1
2.9
B
NOTE 4
4.5
4.3
4221848/A 02/2015
TSSOP - 1.2 mm max height
PW0008A
SMALL OUTLINE PACKAGE
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
1
8
0.1
C A
B
5
4
PIN 1 ID
AREA
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
www.ti.com
EXAMPLE BOARD LAYOUT
(5.8)
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
8X (1.5)
8X (0.45)
6X (0.65)
(R
)
TYP
0.05
4221848/A 02/2015
TSSOP - 1.2 mm max height
PW0008A
SMALL OUTLINE PACKAGE
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:10X
1
4
5
8
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
(5.8)
6X (0.65)
8X (0.45)
8X (1.5)
(R
) TYP
0.05
4221848/A 02/2015
TSSOP - 1.2 mm max height
PW0008A
SMALL OUTLINE PACKAGE
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
4
5
8
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
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Document Outline
